Re: Re: [PATCH] RISC-V: Optimized for strided load/store with stride == element width[PR111450]
Committed, thanks Juzhe. -- Li Xu >Thanks a lot. LGTM. > > > >juzhe.zh...@rivai.ai > >From: Li Xu >Date: 2023-09-21 11:12 >To: gcc-patches >CC: kito.cheng; palmer; juzhe.zhong; xuli >Subject: [PATCH] RISC-V: Optimized for strided load/store with stride == >element width[PR111450] >From: xuli > >When stride == element width, vlsse should be optimized into vle.v. >vsse should be optimized into vse.v. > >PR target/111450 > >gcc/ChangeLog: > >*config/riscv/constraints.md (c01): const_int 1. >(c02): const_int 2. >(c04): const_int 4. >(c08): const_int 8. >* config/riscv/predicates.md (vector_eew8_stride_operand): New predicate for >stride operand. >(vector_eew16_stride_operand): Ditto. >(vector_eew32_stride_operand): Ditto. >(vector_eew64_stride_operand): Ditto. >* config/riscv/vector-iterators.md: New iterator for stride operand. >* config/riscv/vector.md: Add stride = element width constraint. > >gcc/testsuite/ChangeLog: > >* gcc.target/riscv/rvv/base/pr111450.c: New test. >--- >gcc/config/riscv/constraints.md | 20 >gcc/config/riscv/predicates.md | 18 >gcc/config/riscv/vector-iterators.md | 87 +++ >gcc/config/riscv/vector.md | 42 +--- >.../gcc.target/riscv/rvv/base/pr111450.c | 100 ++ >5 files changed, 250 insertions(+), 17 deletions(-) >create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111450.c > >diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md >index 3f52bc76f67..964fdd450c9 100644 >--- a/gcc/config/riscv/constraints.md >+++ b/gcc/config/riscv/constraints.md >@@ -45,6 +45,26 @@ > (and (match_code "const_int") > (match_test "ival == 0"))) >+(define_constraint "c01" >+ "Constant value 1." >+ (and (match_code "const_int") >+ (match_test "ival == 1"))) >+ >+(define_constraint "c02" >+ "Constant value 2" >+ (and (match_code "const_int") >+ (match_test "ival == 2"))) >+ >+(define_constraint "c04" >+ "Constant value 4" >+ (and (match_code "const_int") >+ (match_test "ival == 4"))) >+ >+(define_constraint "c08" >+ "Constant value 8" >+ (and (match_code "const_int") >+ (match_test "ival == 8"))) >+ >(define_constraint "K" > "A 5-bit unsigned immediate for CSR access instructions." > (and (match_code "const_int") >diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md >index 4bc7ff2c9d8..7845998e430 100644 >--- a/gcc/config/riscv/predicates.md >+++ b/gcc/config/riscv/predicates.md >@@ -514,6 +514,24 @@ > (ior (match_operand 0 "const_0_operand") > (match_operand 0 "pmode_register_operand"))) >+;; [1, 2, 4, 8] means strided load/store with stride == element width >+(define_special_predicate "vector_eew8_stride_operand" >+ (ior (match_operand 0 "pmode_register_operand") >+ (and (match_code "const_int") >+ (match_test "INTVAL (op) == 1 || INTVAL (op) == 0" >+(define_special_predicate "vector_eew16_stride_operand" >+ (ior (match_operand 0 "pmode_register_operand") >+ (and (match_code "const_int") >+ (match_test "INTVAL (op) == 2 || INTVAL (op) == 0" >+(define_special_predicate "vector_eew32_stride_operand" >+ (ior (match_operand 0 "pmode_register_operand") >+ (and (match_code "const_int") >+ (match_test "INTVAL (op) == 4 || INTVAL (op) == 0" >+(define_special_predicate "vector_eew64_stride_operand" >+ (ior (match_operand 0 "pmode_register_operand") >+ (and (match_code "const_int") >+ (match_test "INTVAL (op) == 8 || INTVAL (op) == 0" >+ >;; A special predicate that doesn't match a particular mode. >(define_special_predicate "vector_any_register_operand" > (match_code "reg")) >diff --git a/gcc/config/riscv/vector-iterators.md >b/gcc/config/riscv/vector-iterators.md >index 73df55a69c8..f85d1cc80d1 100644 >--- a/gcc/config/riscv/vector-iterators.md >+++ b/gcc/config/riscv/vector-iterators.md >@@ -2596,6 +2596,93 @@ > (V512DI "V512BI") >]) >+(define_mode_attr stride_predicate [ >+ (RVVM8QI "vector_eew8_stride_operand") (RVVM4QI >"vector_eew8_stride_operand") >+ (RVVM2QI "vector_eew8_stride_operand") (RV
Re: [PATCH] RISC-V: Optimized for strided load/store with stride == element width[PR111450]
Thanks a lot. LGTM. juzhe.zh...@rivai.ai From: Li Xu Date: 2023-09-21 11:12 To: gcc-patches CC: kito.cheng; palmer; juzhe.zhong; xuli Subject: [PATCH] RISC-V: Optimized for strided load/store with stride == element width[PR111450] From: xuli When stride == element width, vlsse should be optimized into vle.v. vsse should be optimized into vse.v. PR target/111450 gcc/ChangeLog: *config/riscv/constraints.md (c01): const_int 1. (c02): const_int 2. (c04): const_int 4. (c08): const_int 8. * config/riscv/predicates.md (vector_eew8_stride_operand): New predicate for stride operand. (vector_eew16_stride_operand): Ditto. (vector_eew32_stride_operand): Ditto. (vector_eew64_stride_operand): Ditto. * config/riscv/vector-iterators.md: New iterator for stride operand. * config/riscv/vector.md: Add stride = element width constraint. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr111450.c: New test. --- gcc/config/riscv/constraints.md | 20 gcc/config/riscv/predicates.md| 18 gcc/config/riscv/vector-iterators.md | 87 +++ gcc/config/riscv/vector.md| 42 +--- .../gcc.target/riscv/rvv/base/pr111450.c | 100 ++ 5 files changed, 250 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111450.c diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 3f52bc76f67..964fdd450c9 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -45,6 +45,26 @@ (and (match_code "const_int") (match_test "ival == 0"))) +(define_constraint "c01" + "Constant value 1." + (and (match_code "const_int") + (match_test "ival == 1"))) + +(define_constraint "c02" + "Constant value 2" + (and (match_code "const_int") + (match_test "ival == 2"))) + +(define_constraint "c04" + "Constant value 4" + (and (match_code "const_int") + (match_test "ival == 4"))) + +(define_constraint "c08" + "Constant value 8" + (and (match_code "const_int") + (match_test "ival == 8"))) + (define_constraint "K" "A 5-bit unsigned immediate for CSR access instructions." (and (match_code "const_int") diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 4bc7ff2c9d8..7845998e430 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -514,6 +514,24 @@ (ior (match_operand 0 "const_0_operand") (match_operand 0 "pmode_register_operand"))) +;; [1, 2, 4, 8] means strided load/store with stride == element width +(define_special_predicate "vector_eew8_stride_operand" + (ior (match_operand 0 "pmode_register_operand") + (and (match_code "const_int") +(match_test "INTVAL (op) == 1 || INTVAL (op) == 0" +(define_special_predicate "vector_eew16_stride_operand" + (ior (match_operand 0 "pmode_register_operand") + (and (match_code "const_int") +(match_test "INTVAL (op) == 2 || INTVAL (op) == 0" +(define_special_predicate "vector_eew32_stride_operand" + (ior (match_operand 0 "pmode_register_operand") + (and (match_code "const_int") +(match_test "INTVAL (op) == 4 || INTVAL (op) == 0" +(define_special_predicate "vector_eew64_stride_operand" + (ior (match_operand 0 "pmode_register_operand") + (and (match_code "const_int") +(match_test "INTVAL (op) == 8 || INTVAL (op) == 0" + ;; A special predicate that doesn't match a particular mode. (define_special_predicate "vector_any_register_operand" (match_code "reg")) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 73df55a69c8..f85d1cc80d1 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -2596,6 +2596,93 @@ (V512DI "V512BI") ]) +(define_mode_attr stride_predicate [ + (RVVM8QI "vector_eew8_stride_operand") (RVVM4QI "vector_eew8_stride_operand") + (RVVM2QI "vector_eew8_stride_operand") (RVVM1QI "vector_eew8_stride_operand") + (RVVMF2QI "vector_eew8_stride_operand") (RVVMF4QI "vector_eew8_stride_operand") + (RVVMF8QI "vector_eew8_stride_operand") + + (RVVM8HI "vector_eew16_stride_operand") (RVVM4HI "vector_eew16_stride_operand") + (RVVM2HI "vector_eew16_stride_operand") (RVVM1HI "vector_eew16_stride_operand") + (RVVMF2HI "vector_eew16_stride_operand") (RVVMF4HI "vector_e
[PATCH] RISC-V: Optimized for strided load/store with stride == element width[PR111450]
From: xuli When stride == element width, vlsse should be optimized into vle.v. vsse should be optimized into vse.v. PR target/111450 gcc/ChangeLog: *config/riscv/constraints.md (c01): const_int 1. (c02): const_int 2. (c04): const_int 4. (c08): const_int 8. * config/riscv/predicates.md (vector_eew8_stride_operand): New predicate for stride operand. (vector_eew16_stride_operand): Ditto. (vector_eew32_stride_operand): Ditto. (vector_eew64_stride_operand): Ditto. * config/riscv/vector-iterators.md: New iterator for stride operand. * config/riscv/vector.md: Add stride = element width constraint. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr111450.c: New test. --- gcc/config/riscv/constraints.md | 20 gcc/config/riscv/predicates.md| 18 gcc/config/riscv/vector-iterators.md | 87 +++ gcc/config/riscv/vector.md| 42 +--- .../gcc.target/riscv/rvv/base/pr111450.c | 100 ++ 5 files changed, 250 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr111450.c diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 3f52bc76f67..964fdd450c9 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -45,6 +45,26 @@ (and (match_code "const_int") (match_test "ival == 0"))) +(define_constraint "c01" + "Constant value 1." + (and (match_code "const_int") + (match_test "ival == 1"))) + +(define_constraint "c02" + "Constant value 2" + (and (match_code "const_int") + (match_test "ival == 2"))) + +(define_constraint "c04" + "Constant value 4" + (and (match_code "const_int") + (match_test "ival == 4"))) + +(define_constraint "c08" + "Constant value 8" + (and (match_code "const_int") + (match_test "ival == 8"))) + (define_constraint "K" "A 5-bit unsigned immediate for CSR access instructions." (and (match_code "const_int") diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 4bc7ff2c9d8..7845998e430 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -514,6 +514,24 @@ (ior (match_operand 0 "const_0_operand") (match_operand 0 "pmode_register_operand"))) +;; [1, 2, 4, 8] means strided load/store with stride == element width +(define_special_predicate "vector_eew8_stride_operand" + (ior (match_operand 0 "pmode_register_operand") + (and (match_code "const_int") +(match_test "INTVAL (op) == 1 || INTVAL (op) == 0" +(define_special_predicate "vector_eew16_stride_operand" + (ior (match_operand 0 "pmode_register_operand") + (and (match_code "const_int") +(match_test "INTVAL (op) == 2 || INTVAL (op) == 0" +(define_special_predicate "vector_eew32_stride_operand" + (ior (match_operand 0 "pmode_register_operand") + (and (match_code "const_int") +(match_test "INTVAL (op) == 4 || INTVAL (op) == 0" +(define_special_predicate "vector_eew64_stride_operand" + (ior (match_operand 0 "pmode_register_operand") + (and (match_code "const_int") +(match_test "INTVAL (op) == 8 || INTVAL (op) == 0" + ;; A special predicate that doesn't match a particular mode. (define_special_predicate "vector_any_register_operand" (match_code "reg")) diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 73df55a69c8..f85d1cc80d1 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -2596,6 +2596,93 @@ (V512DI "V512BI") ]) +(define_mode_attr stride_predicate [ + (RVVM8QI "vector_eew8_stride_operand") (RVVM4QI "vector_eew8_stride_operand") + (RVVM2QI "vector_eew8_stride_operand") (RVVM1QI "vector_eew8_stride_operand") + (RVVMF2QI "vector_eew8_stride_operand") (RVVMF4QI "vector_eew8_stride_operand") + (RVVMF8QI "vector_eew8_stride_operand") + + (RVVM8HI "vector_eew16_stride_operand") (RVVM4HI "vector_eew16_stride_operand") + (RVVM2HI "vector_eew16_stride_operand") (RVVM1HI "vector_eew16_stride_operand") + (RVVMF2HI "vector_eew16_stride_operand") (RVVMF4HI "vector_eew16_stride_operand") + + (RVVM8HF "vector_eew16_stride_operand") (RVVM4HF "vector_eew16_stride_operand") + (RVVM2HF "vector_eew16_stride_operand") (RVVM1HF "vector_eew16_stride_operand") + (RVVMF2HF "vector_eew16_stride_operand") (RVVMF4HF "vector_eew16_stride_operand") + + (RVVM8SI "vector_eew32_stride_operand") (RVVM4SI "vector_eew32_stride_operand") + (RVVM2SI "vector_eew32_stride_operand") (RVVM1SI "vector_eew32_stride_operand") + (RVVMF2SI "vector_eew32_stride_operand") + + (RVVM8SF "vector_eew32_stride_operand") (RVVM4SF "vector_eew32_stride_operand") + (RVVM2SF "vector_eew32_stride_operand") (RVVM1SF "vector_eew32_stride_operand") + (RVVMF2SF
