RE: [PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill

2023-06-03 Thread Li, Pan2 via Gcc-patches 
Committed, thanks Kito.

Pan

From: Kito Cheng 
Sent: Sunday, June 4, 2023 9:01 AM
To: Li, Pan2 
Cc: 钟居哲 ; gcc-patches ; 
kito.cheng ; Wang, Yanzhang 
Subject: Re: [PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill

LGTM

Li, Pan2 via Gcc-patches 
mailto:gcc-patches@gcc.gnu.org>> 於 2023年6月4日 週日 08:36 
寫道：
Great! Thanks Juzhe and let’s wait kito’s approval.

Pan

From: 钟居哲 mailto:juzhe.zh...@rivai.ai>>
Sent: Sunday, June 4, 2023 7:36 AM
To: Li, Pan2 mailto:pan2...@intel.com>>; gcc-patches 
mailto:gcc-patches@gcc.gnu.org>>
Cc: kito.cheng mailto:kito.ch...@sifive.com>>; Li, Pan2 
mailto:pan2...@intel.com>>; Wang, Yanzhang 
mailto:yanzhang.w...@intel.com>>
Subject: Re: [PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill

LGTM. Hope FP16 vector can be committed soon.
Since I would like to wait for FP16 vector and then start to support FP16 FP32 
FP64 autovec together.

Thanks.

juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai><mailto:juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>>

From: 
pan2.li<http://pan2.li><mailto:pan2...@intel.com<mailto:pan2...@intel.com>>
Date: 2023-06-03 22:37
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>
CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>>; 
kito.cheng<mailto:kito.ch...@sifive.com<mailto:kito.ch...@sifive.com>>; 
pan2.li<http://pan2.li><mailto:pan2...@intel.com<mailto:pan2...@intel.com>>; 
yanzhang.wang<mailto:yanzhang.w...@intel.com<mailto:yanzhang.w...@intel.com>>
Subject: [PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill
From: Pan Li 
mailto:pan2...@intel.com><mailto:pan2...@intel.com<mailto:pan2...@intel.com>>>

This patch would like to allow the mov and spill operation for the RVV
vfloat16*_t types. The involved machine mode includes VNx1HF, VNx2HF,
VNx4HF, VNx8HF, VNx16HF, VNx32HF and VNx64HF.

Signed-off-by: Pan Li 
mailto:pan2...@intel.com><mailto:pan2...@intel.com<mailto:pan2...@intel.com>>>
Co-Authored by: Juzhe-Zhong 
mailto:juzhe.zh...@rivai.ai><mailto:juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>>>

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-types.def
(vfloat16mf4_t): Add the float16 type to DEF_RVV_F_OPS.
(vfloat16mf2_t): Likewise.
(vfloat16m1_t): Likewise.
(vfloat16m2_t): Likewise.
(vfloat16m4_t): Likewise.
(vfloat16m8_t): Likewise.
* config/riscv/riscv.md: Add vfloat16*_t to attr mode.
* config/riscv/vector-iterators.md: Add vfloat16*_t machine mode
to V, V_WHOLE, V_FRACT, VINDEX, VM, VEL and sew.
* config/riscv/vector.md: Add vfloat16*_t machine mode to sew,
vlmul and ratio.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/mov-14.c: New test.
* gcc.target/riscv/rvv/base/spill-13.c: New test.
---
.../riscv/riscv-vector-builtins-types.def |   7 ++
gcc/config/riscv/riscv.md |   1 +
gcc/config/riscv/vector-iterators.md  |  25 
gcc/config/riscv/vector.md|  35 ++
.../gcc.target/riscv/rvv/base/mov-14.c|  81 +
.../gcc.target/riscv/rvv/base/spill-13.c  | 108 ++
6 files changed, 257 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-13.c

diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def 
b/gcc/config/riscv/riscv-vector-builtins-types.def
index f7f650f7e95..65716b8c637 100644
--- a/gcc/config/riscv/riscv-vector-builtins-types.def
+++ b/gcc/config/riscv/riscv-vector-builtins-types.def
@@ -385,6 +385,13 @@ DEF_RVV_U_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_U_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_U_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_F_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_F_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m8_t, RVV_REQUIRE_ELEN_FP_16)
+
DEF_RVV_F_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_F_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_F_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index f545874edc1..be960583101 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -175,6 +175,7 @@ (define_attr "mode" 
"unknown,none,QI,HI,SI,DI,TI,HF,SF,DF,TF,
   VNx1HI,VNx2HI,VNx4HI,VNx8HI,VNx16HI,VNx32HI,VNx64HI,
   VNx1SI,VNx2SI,VNx4SI,VNx8SI,VNx16SI,VNx32SI,
   VNx1DI,VNx2DI,VNx4DI,VNx8DI,VNx16DI,
+  VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF,
   VNx1SF,VNx2SF,VNx4SF,VNx8SF,VNx16SF,VNx32SF,
   VNx1DF,VNx2DF,VNx4DF,VNx8

Re: [PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill

2023-06-03 Thread Kito Cheng via Gcc-patches 
LGTM

Li, Pan2 via Gcc-patches  於 2023年6月4日 週日 08:36 寫道：

> Great! Thanks Juzhe and let’s wait kito’s approval.
>
> Pan
>
> From: 钟居哲 
> Sent: Sunday, June 4, 2023 7:36 AM
> To: Li, Pan2 ; gcc-patches 
> Cc: kito.cheng ; Li, Pan2 ;
> Wang, Yanzhang 
> Subject: Re: [PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and
> spill
>
> LGTM. Hope FP16 vector can be committed soon.
> Since I would like to wait for FP16 vector and then start to support FP16
> FP32 FP64 autovec together.
>
> Thanks.
> 
> juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>
>
> From: pan2.li<mailto:pan2...@intel.com>
> Date: 2023-06-03 22:37
> To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
> CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>; kito.cheng kito.ch...@sifive.com>; pan2.li<mailto:pan2...@intel.com>;
> yanzhang.wang<mailto:yanzhang.w...@intel.com>
> Subject: [PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill
> From: Pan Li mailto:pan2...@intel.com>>
>
> This patch would like to allow the mov and spill operation for the RVV
> vfloat16*_t types. The involved machine mode includes VNx1HF, VNx2HF,
> VNx4HF, VNx8HF, VNx16HF, VNx32HF and VNx64HF.
>
> Signed-off-by: Pan Li mailto:pan2...@intel.com>>
> Co-Authored by: Juzhe-Zhong  juzhe.zh...@rivai.ai>>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-types.def
> (vfloat16mf4_t): Add the float16 type to DEF_RVV_F_OPS.
> (vfloat16mf2_t): Likewise.
> (vfloat16m1_t): Likewise.
> (vfloat16m2_t): Likewise.
> (vfloat16m4_t): Likewise.
> (vfloat16m8_t): Likewise.
> * config/riscv/riscv.md: Add vfloat16*_t to attr mode.
> * config/riscv/vector-iterators.md: Add vfloat16*_t machine mode
> to V, V_WHOLE, V_FRACT, VINDEX, VM, VEL and sew.
> * config/riscv/vector.md: Add vfloat16*_t machine mode to sew,
> vlmul and ratio.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/mov-14.c: New test.
> * gcc.target/riscv/rvv/base/spill-13.c: New test.
> ---
> .../riscv/riscv-vector-builtins-types.def |   7 ++
> gcc/config/riscv/riscv.md |   1 +
> gcc/config/riscv/vector-iterators.md  |  25 
> gcc/config/riscv/vector.md|  35 ++
> .../gcc.target/riscv/rvv/base/mov-14.c|  81 +
> .../gcc.target/riscv/rvv/base/spill-13.c  | 108 ++
> 6 files changed, 257 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-14.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-13.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def
> b/gcc/config/riscv/riscv-vector-builtins-types.def
> index f7f650f7e95..65716b8c637 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-types.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-types.def
> @@ -385,6 +385,13 @@ DEF_RVV_U_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
> DEF_RVV_U_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
> DEF_RVV_U_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
> +DEF_RVV_F_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 |
> RVV_REQUIRE_MIN_VLEN_64)
> +DEF_RVV_F_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_F_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_F_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_F_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_F_OPS (vfloat16m8_t, RVV_REQUIRE_ELEN_FP_16)
> +
> DEF_RVV_F_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 |
> RVV_REQUIRE_MIN_VLEN_64)
> DEF_RVV_F_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
> DEF_RVV_F_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index f545874edc1..be960583101 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -175,6 +175,7 @@ (define_attr "mode"
> "unknown,none,QI,HI,SI,DI,TI,HF,SF,DF,TF,
>VNx1HI,VNx2HI,VNx4HI,VNx8HI,VNx16HI,VNx32HI,VNx64HI,
>VNx1SI,VNx2SI,VNx4SI,VNx8SI,VNx16SI,VNx32SI,
>VNx1DI,VNx2DI,VNx4DI,VNx8DI,VNx16DI,
> +  VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF,
>VNx1SF,VNx2SF,VNx4SF,VNx8SF,VNx16SF,VNx32SF,
>VNx1DF,VNx2DF,VNx4DF,VNx8DF,VNx16DF,
>VNx2x64QI,VNx2x32QI,VNx3x32QI,VNx4x32QI,
> diff --git a/gcc/config/riscv/vector-iterators.md
> b/gcc/config/riscv/vector-iterators.md
> index 937ec3c7f67..5fbaef89566 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -90,6 +90,15 @@ (define_mode_iterator V [
>(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI
> "TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128")
>(VNx1DI "TARGET_VECTO

RE: [PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill

2023-06-03 Thread Li, Pan2 via Gcc-patches 
Great! Thanks Juzhe and let’s wait kito’s approval.

Pan

From: 钟居哲 
Sent: Sunday, June 4, 2023 7:36 AM
To: Li, Pan2 ; gcc-patches 
Cc: kito.cheng ; Li, Pan2 ; Wang, 
Yanzhang 
Subject: Re: [PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill

LGTM. Hope FP16 vector can be committed soon.
Since I would like to wait for FP16 vector and then start to support FP16 FP32 
FP64 autovec together.

Thanks.

juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>

From: pan2.li<mailto:pan2...@intel.com>
Date: 2023-06-03 22:37
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>; 
kito.cheng<mailto:kito.ch...@sifive.com>; pan2.li<mailto:pan2...@intel.com>; 
yanzhang.wang<mailto:yanzhang.w...@intel.com>
Subject: [PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill
From: Pan Li mailto:pan2...@intel.com>>

This patch would like to allow the mov and spill operation for the RVV
vfloat16*_t types. The involved machine mode includes VNx1HF, VNx2HF,
VNx4HF, VNx8HF, VNx16HF, VNx32HF and VNx64HF.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>
Co-Authored by: Juzhe-Zhong mailto:juzhe.zh...@rivai.ai>>

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-types.def
(vfloat16mf4_t): Add the float16 type to DEF_RVV_F_OPS.
(vfloat16mf2_t): Likewise.
(vfloat16m1_t): Likewise.
(vfloat16m2_t): Likewise.
(vfloat16m4_t): Likewise.
(vfloat16m8_t): Likewise.
* config/riscv/riscv.md: Add vfloat16*_t to attr mode.
* config/riscv/vector-iterators.md: Add vfloat16*_t machine mode
to V, V_WHOLE, V_FRACT, VINDEX, VM, VEL and sew.
* config/riscv/vector.md: Add vfloat16*_t machine mode to sew,
vlmul and ratio.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/mov-14.c: New test.
* gcc.target/riscv/rvv/base/spill-13.c: New test.
---
.../riscv/riscv-vector-builtins-types.def |   7 ++
gcc/config/riscv/riscv.md |   1 +
gcc/config/riscv/vector-iterators.md  |  25 
gcc/config/riscv/vector.md|  35 ++
.../gcc.target/riscv/rvv/base/mov-14.c|  81 +
.../gcc.target/riscv/rvv/base/spill-13.c  | 108 ++
6 files changed, 257 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-13.c

diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def 
b/gcc/config/riscv/riscv-vector-builtins-types.def
index f7f650f7e95..65716b8c637 100644
--- a/gcc/config/riscv/riscv-vector-builtins-types.def
+++ b/gcc/config/riscv/riscv-vector-builtins-types.def
@@ -385,6 +385,13 @@ DEF_RVV_U_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_U_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_U_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_F_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_F_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m8_t, RVV_REQUIRE_ELEN_FP_16)
+
DEF_RVV_F_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_F_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_F_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index f545874edc1..be960583101 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -175,6 +175,7 @@ (define_attr "mode" 
"unknown,none,QI,HI,SI,DI,TI,HF,SF,DF,TF,
   VNx1HI,VNx2HI,VNx4HI,VNx8HI,VNx16HI,VNx32HI,VNx64HI,
   VNx1SI,VNx2SI,VNx4SI,VNx8SI,VNx16SI,VNx32SI,
   VNx1DI,VNx2DI,VNx4DI,VNx8DI,VNx16DI,
+  VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF,
   VNx1SF,VNx2SF,VNx4SF,VNx8SF,VNx16SF,VNx32SF,
   VNx1DF,VNx2DF,VNx4DF,VNx8DF,VNx16DF,
   VNx2x64QI,VNx2x32QI,VNx3x32QI,VNx4x32QI,
diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index 937ec3c7f67..5fbaef89566 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -90,6 +90,15 @@ (define_mode_iterator V [
   (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI 
"TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128")
   (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI 
"TARGET_VECTOR_ELEN_64")
   (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI 
"TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
+
+  (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+  (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx16HF "TARGET_VECTOR_ELEN_FP_16"

Re: [PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill

2023-06-03 Thread 钟居哲 
LGTM. Hope FP16 vector can be committed soon.
Since I would like to wait for FP16 vector and then start to support FP16 FP32 
FP64 autovec together.

Thanks.


juzhe.zh...@rivai.ai
 
From: pan2.li
Date: 2023-06-03 22:37
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject: [PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill
From: Pan Li 
 
This patch would like to allow the mov and spill operation for the RVV
vfloat16*_t types. The involved machine mode includes VNx1HF, VNx2HF,
VNx4HF, VNx8HF, VNx16HF, VNx32HF and VNx64HF.
 
Signed-off-by: Pan Li 
Co-Authored by: Juzhe-Zhong 
 
gcc/ChangeLog:
 
* config/riscv/riscv-vector-builtins-types.def
(vfloat16mf4_t): Add the float16 type to DEF_RVV_F_OPS.
(vfloat16mf2_t): Likewise.
(vfloat16m1_t): Likewise.
(vfloat16m2_t): Likewise.
(vfloat16m4_t): Likewise.
(vfloat16m8_t): Likewise.
* config/riscv/riscv.md: Add vfloat16*_t to attr mode.
* config/riscv/vector-iterators.md: Add vfloat16*_t machine mode
to V, V_WHOLE, V_FRACT, VINDEX, VM, VEL and sew.
* config/riscv/vector.md: Add vfloat16*_t machine mode to sew,
vlmul and ratio.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/base/mov-14.c: New test.
* gcc.target/riscv/rvv/base/spill-13.c: New test.
---
.../riscv/riscv-vector-builtins-types.def |   7 ++
gcc/config/riscv/riscv.md |   1 +
gcc/config/riscv/vector-iterators.md  |  25 
gcc/config/riscv/vector.md|  35 ++
.../gcc.target/riscv/rvv/base/mov-14.c|  81 +
.../gcc.target/riscv/rvv/base/spill-13.c  | 108 ++
6 files changed, 257 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-14.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-13.c
 
diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def 
b/gcc/config/riscv/riscv-vector-builtins-types.def
index f7f650f7e95..65716b8c637 100644
--- a/gcc/config/riscv/riscv-vector-builtins-types.def
+++ b/gcc/config/riscv/riscv-vector-builtins-types.def
@@ -385,6 +385,13 @@ DEF_RVV_U_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_U_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
DEF_RVV_U_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
+DEF_RVV_F_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_F_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m8_t, RVV_REQUIRE_ELEN_FP_16)
+
DEF_RVV_F_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
DEF_RVV_F_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
DEF_RVV_F_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index f545874edc1..be960583101 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -175,6 +175,7 @@ (define_attr "mode" 
"unknown,none,QI,HI,SI,DI,TI,HF,SF,DF,TF,
   VNx1HI,VNx2HI,VNx4HI,VNx8HI,VNx16HI,VNx32HI,VNx64HI,
   VNx1SI,VNx2SI,VNx4SI,VNx8SI,VNx16SI,VNx32SI,
   VNx1DI,VNx2DI,VNx4DI,VNx8DI,VNx16DI,
+  VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF,
   VNx1SF,VNx2SF,VNx4SF,VNx8SF,VNx16SF,VNx32SF,
   VNx1DF,VNx2DF,VNx4DF,VNx8DF,VNx16DF,
   VNx2x64QI,VNx2x32QI,VNx3x32QI,VNx4x32QI,
diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index 937ec3c7f67..5fbaef89566 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -90,6 +90,15 @@ (define_mode_iterator V [
   (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI 
"TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128")
   (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI 
"TARGET_VECTOR_ELEN_64")
   (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI 
"TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
+
+  (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+  (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+  (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
   (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
   (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
   (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
@@ -427,6 +436,15 @@ (define_mode_iterator V_WHOLE [
   (VNx1SI "TARGET_MIN_VLEN == 32") VNx2SI VNx4SI VNx8SI (VNx16SI 
"TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128")
   (VNx1DI "TARGET_VECTOR_ELEN_64 &&

[PATCH] RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill

2023-06-03 Thread Pan Li via Gcc-patches 
From: Pan Li 

This patch would like to allow the mov and spill operation for the RVV
vfloat16*_t types. The involved machine mode includes VNx1HF, VNx2HF,
VNx4HF, VNx8HF, VNx16HF, VNx32HF and VNx64HF.

Signed-off-by: Pan Li 
Co-Authored by: Juzhe-Zhong 

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-types.def
(vfloat16mf4_t): Add the float16 type to DEF_RVV_F_OPS.
(vfloat16mf2_t): Likewise.
(vfloat16m1_t): Likewise.
(vfloat16m2_t): Likewise.
(vfloat16m4_t): Likewise.
(vfloat16m8_t): Likewise.
* config/riscv/riscv.md: Add vfloat16*_t to attr mode.
* config/riscv/vector-iterators.md: Add vfloat16*_t machine mode
to V, V_WHOLE, V_FRACT, VINDEX, VM, VEL and sew.
* config/riscv/vector.md: Add vfloat16*_t machine mode to sew,
vlmul and ratio.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/mov-14.c: New test.
* gcc.target/riscv/rvv/base/spill-13.c: New test.
---
 .../riscv/riscv-vector-builtins-types.def |   7 ++
 gcc/config/riscv/riscv.md |   1 +
 gcc/config/riscv/vector-iterators.md  |  25 
 gcc/config/riscv/vector.md|  35 ++
 .../gcc.target/riscv/rvv/base/mov-14.c|  81 +
 .../gcc.target/riscv/rvv/base/spill-13.c  | 108 ++
 6 files changed, 257 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/mov-14.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-13.c

diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def 
b/gcc/config/riscv/riscv-vector-builtins-types.def
index f7f650f7e95..65716b8c637 100644
--- a/gcc/config/riscv/riscv-vector-builtins-types.def
+++ b/gcc/config/riscv/riscv-vector-builtins-types.def
@@ -385,6 +385,13 @@ DEF_RVV_U_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
 DEF_RVV_U_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
 DEF_RVV_U_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
 
+DEF_RVV_F_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 | RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_F_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16)
+DEF_RVV_F_OPS (vfloat16m8_t, RVV_REQUIRE_ELEN_FP_16)
+
 DEF_RVV_F_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 | RVV_REQUIRE_MIN_VLEN_64)
 DEF_RVV_F_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
 DEF_RVV_F_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index f545874edc1..be960583101 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -175,6 +175,7 @@ (define_attr "mode" 
"unknown,none,QI,HI,SI,DI,TI,HF,SF,DF,TF,
   VNx1HI,VNx2HI,VNx4HI,VNx8HI,VNx16HI,VNx32HI,VNx64HI,
   VNx1SI,VNx2SI,VNx4SI,VNx8SI,VNx16SI,VNx32SI,
   VNx1DI,VNx2DI,VNx4DI,VNx8DI,VNx16DI,
+  VNx1HF,VNx2HF,VNx4HF,VNx8HF,VNx16HF,VNx32HF,VNx64HF,
   VNx1SF,VNx2SF,VNx4SF,VNx8SF,VNx16SF,VNx32SF,
   VNx1DF,VNx2DF,VNx4DF,VNx8DF,VNx16DF,
   VNx2x64QI,VNx2x32QI,VNx3x32QI,VNx4x32QI,
diff --git a/gcc/config/riscv/vector-iterators.md 
b/gcc/config/riscv/vector-iterators.md
index 937ec3c7f67..5fbaef89566 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -90,6 +90,15 @@ (define_mode_iterator V [
   (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI VNx8SI (VNx16SI 
"TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128")
   (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI 
"TARGET_VECTOR_ELEN_64")
   (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI 
"TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
+
+  (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+  (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+  (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
   (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
   (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
   (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
@@ -427,6 +436,15 @@ (define_mode_iterator V_WHOLE [
   (VNx1SI "TARGET_MIN_VLEN == 32") VNx2SI VNx4SI VNx8SI (VNx16SI 
"TARGET_MIN_VLEN > 32") (VNx32SI "TARGET_MIN_VLEN >= 128")
   (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI 
"TARGET_VECTOR_ELEN_64")
   (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx8DI "TARGET_VECTOR_ELEN_64") (VNx16DI 
"TARGET_MIN_VLEN >= 128")
+
+  (VNx1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128")
+  (VNx2HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx4HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx8HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx16HF "TARGET_VECTOR_ELEN_FP_16")
+  (VNx32HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
+  (VNx64HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
+
   (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN