[PATCH] RISC-V: add option -m(no-)autovec-segment
LGTM juzhe.zh...@rivai.ai
Re: [PATCH] RISC-V: add option -m(no-)autovec-segment
On 2/27/24 07:25, Jeff Law wrote: > On 2/25/24 21:53, Greg McGary wrote: >> Add option -m(no-)autovec-segment to enable/disable autovectorizer >> from emitting vector segment load/store instructions. This is useful for >> performance experiments. >> >> gcc/ChangeLog: >> * config/riscv/autovec.md (vec_mask_len_load_lanes, >> vec_mask_len_store_lanes): >>Predicate with TARGET_VECTOR_AUTOVEC_SEGMENT >> * gcc/config/riscv/riscv-opts.h (TARGET_VECTOR_AUTOVEC_SEGMENT): New >> macro. >> * gcc/config/riscv/riscv.opt (-m(no-)autovec-segment): New option. >> * gcc/tree-vect-stmts.cc (gcc/tree-vect-stmts.cc): Prevent >> divide-by-zero. >> * testsuite/gcc.target/riscv/rvv/autovec/struct/*_noseg*.c, >> testsuite/gcc.target/riscv/rvv/autovec/no-segment.c: New tests. > I don't mind having options to do this kind of selection (we've done > similar things internally for other RVV features). But I don't think > now is the time to be introducing this stuff. We're in stage4 of the > development cycle after all. Ping ! now that we are back in stage1 Thx, -Vineet
Re: [PATCH] RISC-V: add option -m(no-)autovec-segment
On 2/27/24 13:30, Greg McGary wrote:
On 2/27/24 8:25 AM, Jeff Law wrote:
On 2/25/24 21:53, Greg McGary wrote:
Add option -m(no-)autovec-segment to enable/disable autovectorizer
from emitting vector segment load/store instructions. This is useful for
performance experiments.
gcc/ChangeLog:
* config/riscv/autovec.md (vec_mask_len_load_lanes,
vec_mask_len_store_lanes):
Predicate with TARGET_VECTOR_AUTOVEC_SEGMENT
* gcc/config/riscv/riscv-opts.h (TARGET_VECTOR_AUTOVEC_SEGMENT):
New macro.
* gcc/config/riscv/riscv.opt (-m(no-)autovec-segment): New option.
* gcc/tree-vect-stmts.cc (gcc/tree-vect-stmts.cc): Prevent
divide-by-zero.
* testsuite/gcc.target/riscv/rvv/autovec/struct/*_noseg*.c,
testsuite/gcc.target/riscv/rvv/autovec/no-segment.c: New tests.
I don't mind having options to do this kind of selection (we've done
similar things internally for other RVV features). But I don't think
now is the time to be introducing this stuff. We're in stage4 of the
development cycle after all.
No problemo. Will you take the simple bugfix?
gcc/tree-vect-stmts.cc (gcc/tree-vect-stmts.cc): Prevent divide-by-zero.
diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc
index 1dbe1115da4..6303d82d959 100644
--- a/gcc/tree-vect-stmts.cc
+++ b/gcc/tree-vect-stmts.cc
@@ -11521,7 +11521,8 @@ vectorizable_load (vec_info *vinfo,
- (vec_num * j + i) * nunits);
/* remain should now be > 0 and < nunits. */
unsigned num;
- if (constant_multiple_p (nunits, remain, ))
+ if (known_gt (remain, 0)
+ && constant_multiple_p (nunits, remain, ))
{
tree ptype;
new_vtype
I am unaware of a testcase that triggers it without disabling segmented
load, so LMK if you are cool with the fix without a test case.
We'd really need a testcase and some analysis -- this change will affect
every target, so you'd need to explain why the change is correct.
jeff
Re: [PATCH] RISC-V: add option -m(no-)autovec-segment
On 2/27/24 8:25 AM, Jeff Law wrote:
On 2/25/24 21:53, Greg McGary wrote:
Add option -m(no-)autovec-segment to enable/disable autovectorizer
from emitting vector segment load/store instructions. This is useful for
performance experiments.
gcc/ChangeLog:
* config/riscv/autovec.md (vec_mask_len_load_lanes,
vec_mask_len_store_lanes):
Predicate with TARGET_VECTOR_AUTOVEC_SEGMENT
* gcc/config/riscv/riscv-opts.h (TARGET_VECTOR_AUTOVEC_SEGMENT):
New macro.
* gcc/config/riscv/riscv.opt (-m(no-)autovec-segment): New option.
* gcc/tree-vect-stmts.cc (gcc/tree-vect-stmts.cc): Prevent
divide-by-zero.
* testsuite/gcc.target/riscv/rvv/autovec/struct/*_noseg*.c,
testsuite/gcc.target/riscv/rvv/autovec/no-segment.c: New tests.
I don't mind having options to do this kind of selection (we've done
similar things internally for other RVV features). But I don't think
now is the time to be introducing this stuff. We're in stage4 of the
development cycle after all.
No problemo. Will you take the simple bugfix?
gcc/tree-vect-stmts.cc (gcc/tree-vect-stmts.cc): Prevent divide-by-zero.
diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc
index 1dbe1115da4..6303d82d959 100644
--- a/gcc/tree-vect-stmts.cc
+++ b/gcc/tree-vect-stmts.cc
@@ -11521,7 +11521,8 @@ vectorizable_load (vec_info *vinfo,
- (vec_num * j + i) * nunits);
/* remain should now be > 0 and < nunits. */
unsigned num;
- if (constant_multiple_p (nunits, remain, ))
+ if (known_gt (remain, 0)
+ && constant_multiple_p (nunits, remain, ))
{
tree ptype;
new_vtype
I am unaware of a testcase that triggers it without disabling segmented
load,
so LMK if you are cool with the fix without a test case.
G
Re: [PATCH] RISC-V: add option -m(no-)autovec-segment
On 2/25/24 21:53, Greg McGary wrote: Add option -m(no-)autovec-segment to enable/disable autovectorizer from emitting vector segment load/store instructions. This is useful for performance experiments. gcc/ChangeLog: * config/riscv/autovec.md (vec_mask_len_load_lanes, vec_mask_len_store_lanes): Predicate with TARGET_VECTOR_AUTOVEC_SEGMENT * gcc/config/riscv/riscv-opts.h (TARGET_VECTOR_AUTOVEC_SEGMENT): New macro. * gcc/config/riscv/riscv.opt (-m(no-)autovec-segment): New option. * gcc/tree-vect-stmts.cc (gcc/tree-vect-stmts.cc): Prevent divide-by-zero. * testsuite/gcc.target/riscv/rvv/autovec/struct/*_noseg*.c, testsuite/gcc.target/riscv/rvv/autovec/no-segment.c: New tests. I don't mind having options to do this kind of selection (we've done similar things internally for other RVV features). But I don't think now is the time to be introducing this stuff. We're in stage4 of the development cycle after all. jeff
[PATCH] RISC-V: add option -m(no-)autovec-segment
diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc
index 1dbe1115da4..6303d82d959 100644
--- a/gcc/tree-vect-stmts.cc
+++ b/gcc/tree-vect-stmts.cc
@@ -11521,7 +11521,8 @@ vectorizable_load (vec_info *vinfo,
- (vec_num * j + i) * nunits);
/* remain should now be > 0 and < nunits. */
unsigned num;
- if (constant_multiple_p (nunits, remain, ))
+ if (known_gt (remain, 0)
+ && constant_multiple_p (nunits, remain, ))
Why do you change loop vectorize code here ？
Ideally, we should add cost model for segment load/store instead of disable
segment load/store autovectorization with compile option.
with this recognition like aarch64:
/* Return true if an access of kind KIND for STMT_INFO represents one
vector of an LD[234] or ST[234] operation. Return the total number of
vectors (2, 3 or 4) if so, otherwise return a value outside that range. */
static int
aarch64_ld234_st234_vectors (vect_cost_for_stmt kind, stmt_vec_info stmt_info)
{
if ((kind == vector_load
|| kind == unaligned_load
|| kind == vector_store
|| kind == unaligned_store)
&& STMT_VINFO_DATA_REF (stmt_info))
{
stmt_info = DR_GROUP_FIRST_ELEMENT (stmt_info);
if (stmt_info
&& STMT_VINFO_MEMORY_ACCESS_TYPE (stmt_info) == VMAT_LOAD_STORE_LANES)
return DR_GROUP_SIZE (stmt_info);
}
return 0;
}
juzhe.zh...@rivai.ai
[PATCH] RISC-V: add option -m(no-)autovec-segment
Add option -m(no-)autovec-segment to enable/disable autovectorizer from emitting vector segment load/store instructions. This is useful for performance experiments. gcc/ChangeLog: * config/riscv/autovec.md (vec_mask_len_load_lanes, vec_mask_len_store_lanes): Predicate with TARGET_VECTOR_AUTOVEC_SEGMENT * gcc/config/riscv/riscv-opts.h (TARGET_VECTOR_AUTOVEC_SEGMENT): New macro. * gcc/config/riscv/riscv.opt (-m(no-)autovec-segment): New option. * gcc/tree-vect-stmts.cc (gcc/tree-vect-stmts.cc): Prevent divide-by-zero. * testsuite/gcc.target/riscv/rvv/autovec/struct/*_noseg*.c, testsuite/gcc.target/riscv/rvv/autovec/no-segment.c: New tests. --- gcc/config/riscv/autovec.md | 4 +- gcc/config/riscv/riscv-opts.h | 5 ++ gcc/config/riscv/riscv.opt| 4 ++ .../gcc.target/riscv/rvv/autovec/no-segment.c | 61 +++ .../autovec/struct/mask_struct_load_noseg-1.c | 6 ++ .../autovec/struct/mask_struct_load_noseg-2.c | 6 ++ .../autovec/struct/mask_struct_load_noseg-3.c | 6 ++ .../autovec/struct/mask_struct_load_noseg-4.c | 6 ++ .../autovec/struct/mask_struct_load_noseg-5.c | 6 ++ .../autovec/struct/mask_struct_load_noseg-6.c | 6 ++ .../autovec/struct/mask_struct_load_noseg-7.c | 6 ++ .../struct/mask_struct_load_noseg_run-1.c | 4 ++ .../struct/mask_struct_load_noseg_run-2.c | 4 ++ .../struct/mask_struct_load_noseg_run-3.c | 4 ++ .../struct/mask_struct_load_noseg_run-4.c | 4 ++ .../struct/mask_struct_load_noseg_run-5.c | 4 ++ .../struct/mask_struct_load_noseg_run-6.c | 4 ++ .../struct/mask_struct_load_noseg_run-7.c | 4 ++ .../struct/mask_struct_store_noseg-1.c| 6 ++ .../struct/mask_struct_store_noseg-2.c| 6 ++ .../struct/mask_struct_store_noseg-3.c| 6 ++ .../struct/mask_struct_store_noseg-4.c| 6 ++ .../struct/mask_struct_store_noseg-5.c| 6 ++ .../struct/mask_struct_store_noseg-6.c| 6 ++ .../struct/mask_struct_store_noseg-7.c| 6 ++ .../struct/mask_struct_store_noseg_run-1.c| 4 ++ .../struct/mask_struct_store_noseg_run-2.c| 4 ++ .../struct/mask_struct_store_noseg_run-3.c| 4 ++ .../struct/mask_struct_store_noseg_run-4.c| 4 ++ .../struct/mask_struct_store_noseg_run-5.c| 4 ++ .../struct/mask_struct_store_noseg_run-6.c| 4 ++ .../struct/mask_struct_store_noseg_run-7.c| 4 ++ .../rvv/autovec/struct/struct_vect_noseg-1.c | 8 +++ .../rvv/autovec/struct/struct_vect_noseg-10.c | 7 +++ .../rvv/autovec/struct/struct_vect_noseg-11.c | 7 +++ .../rvv/autovec/struct/struct_vect_noseg-12.c | 7 +++ .../rvv/autovec/struct/struct_vect_noseg-13.c | 6 ++ .../rvv/autovec/struct/struct_vect_noseg-14.c | 6 ++ .../rvv/autovec/struct/struct_vect_noseg-15.c | 6 ++ .../rvv/autovec/struct/struct_vect_noseg-16.c | 6 ++ .../rvv/autovec/struct/struct_vect_noseg-17.c | 6 ++ .../rvv/autovec/struct/struct_vect_noseg-18.c | 6 ++ .../rvv/autovec/struct/struct_vect_noseg-2.c | 8 +++ .../rvv/autovec/struct/struct_vect_noseg-3.c | 8 +++ .../rvv/autovec/struct/struct_vect_noseg-4.c | 8 +++ .../rvv/autovec/struct/struct_vect_noseg-5.c | 8 +++ .../rvv/autovec/struct/struct_vect_noseg-6.c | 7 +++ .../rvv/autovec/struct/struct_vect_noseg-7.c | 7 +++ .../rvv/autovec/struct/struct_vect_noseg-8.c | 7 +++ .../rvv/autovec/struct/struct_vect_noseg-9.c | 7 +++ .../autovec/struct/struct_vect_noseg_run-1.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-10.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-11.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-12.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-13.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-14.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-15.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-16.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-17.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-18.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-2.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-3.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-4.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-5.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-6.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-7.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-8.c | 4 ++ .../autovec/struct/struct_vect_noseg_run-9.c | 4 ++ gcc/tree-vect-stmts.cc| 3 +- 69 files changed, 411 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/no-segment.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/struct/mask_struct_load_noseg-3.c create mode 100644
