RE: [PATCH] RISC-V Regression: Fix FAIL of pr65947-8.c for RVV

[Li, Pan2]

Committed, thanks Jeff.

Pan

-Original Message-
From: Jeff Law  
Sent: Tuesday, October 10, 2023 9:24 PM
To: Juzhe-Zhong ; gcc-patches@gcc.gnu.org
Cc: rguent...@suse.de
Subject: Re: [PATCH] RISC-V Regression: Fix FAIL of pr65947-8.c for RVV



On 10/10/23 06:55, Juzhe-Zhong wrote:
> This test is testing fold_extract_last pattern so it's more reasonable use
> vect_fold_extract_last instead of specifying targets.
> 
> This is the vect_fold_extract_last property:
> proc check_effective_target_vect_fold_extract_last { } {
>  return [expr { [check_effective_target_aarch64_sve]
>  || [istarget amdgcn*-*-*]
>  || [check_effective_target_riscv_v] }]
> }
> 
> include ARM SVE/GCN/RVV.
> 
> It perfectly matches what we want and more reasonable, better maintainment.
> 
> gcc/testsuite/ChangeLog:
> 
>   * gcc.dg/vect/pr65947-8.c: Use vect_fold_extract_last.
OK
jeff

Re: [PATCH] RISC-V Regression: Fix FAIL of pr65947-8.c for RVV

[Jeff Law]

On 10/10/23 06:55, Juzhe-Zhong wrote:

This test is testing fold_extract_last pattern so it's more reasonable use
vect_fold_extract_last instead of specifying targets.

This is the vect_fold_extract_last property:
proc check_effective_target_vect_fold_extract_last { } {
 return [expr { [check_effective_target_aarch64_sve]
   || [istarget amdgcn*-*-*]
   || [check_effective_target_riscv_v] }]
}

include ARM SVE/GCN/RVV.

It perfectly matches what we want and more reasonable, better maintainment.

gcc/testsuite/ChangeLog:

* gcc.dg/vect/pr65947-8.c: Use vect_fold_extract_last.

OK
jeff

[PATCH] RISC-V Regression: Fix FAIL of pr65947-8.c for RVV

[Juzhe-Zhong]

This test is testing fold_extract_last pattern so it's more reasonable use
vect_fold_extract_last instead of specifying targets.

This is the vect_fold_extract_last property:
proc check_effective_target_vect_fold_extract_last { } {
return [expr { [check_effective_target_aarch64_sve]
   || [istarget amdgcn*-*-*]
   || [check_effective_target_riscv_v] }]
}

include ARM SVE/GCN/RVV.

It perfectly matches what we want and more reasonable, better maintainment.

gcc/testsuite/ChangeLog:

* gcc.dg/vect/pr65947-8.c: Use vect_fold_extract_last.

---
 gcc/testsuite/gcc.dg/vect/pr65947-8.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.dg/vect/pr65947-8.c 
b/gcc/testsuite/gcc.dg/vect/pr65947-8.c
index d0426792e35..9ced4dbb69f 100644
--- a/gcc/testsuite/gcc.dg/vect/pr65947-8.c
+++ b/gcc/testsuite/gcc.dg/vect/pr65947-8.c
@@ -41,6 +41,6 @@ main (void)
   return 0;
 }
 
-/* { dg-final { scan-tree-dump-not "LOOP VECTORIZED" "vect" { target { ! { 
amdgcn*-*-* || aarch64_sve } } } } } */
-/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" { target { amdgcn*-*-* 
|| aarch64_sve } } } } */
-/* { dg-final { scan-tree-dump "multiple types in double reduction or 
condition reduction" "vect" { target { ! { amdgcn*-*-* || aarch64_sve } } } } } 
*/
+/* { dg-final { scan-tree-dump-not "LOOP VECTORIZED" "vect" { target { ! { 
vect_fold_extract_last } } } } } */
+/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" { target { 
vect_fold_extract_last } } } } */
+/* { dg-final { scan-tree-dump "multiple types in double reduction or 
condition reduction" "vect" { target { ! { vect_fold_extract_last } } } } } */
-- 
2.36.3