PR bootstrap/55211
Revert:
* config/sparc/constraints.md ("U"): Delete.
* config/sparc/sparc.md: Use 'r' constraint instead of 'U'.
* config/sparc/sync.md: Likewise.
And revert parts of:
* doc/md.texi: Sync sparc constraint documentation with reality.
---
gcc/ChangeLog | 10 ++++++++++
gcc/config/sparc/constraints.md | 11 ++++++++++-
gcc/config/sparc/sparc.md | 16 ++++++++--------
gcc/config/sparc/sync.md | 4 ++--
gcc/doc/md.texi | 3 +++
5 files changed, 33 insertions(+), 11 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index eb4bd88..dc62c59 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2012-11-07 David S. Miller <da...@davemloft.net>
+
+ PR bootstrap/55211
+ Revert:
+ * config/sparc/constraints.md ("U"): Delete.
+ * config/sparc/sparc.md: Use 'r' constraint instead of 'U'.
+ * config/sparc/sync.md: Likewise.
+ And revert parts of:
+ * doc/md.texi: Sync sparc constraint documentation with reality.
+
2012-11-07 Jakub Jelinek <ja...@redhat.com>
* config/i386/i386.c (ix86_avx_u128_mode_after): Don't
diff --git a/gcc/config/sparc/constraints.md b/gcc/config/sparc/constraints.md
index 71670ee..2f8c6ad 100644
--- a/gcc/config/sparc/constraints.md
+++ b/gcc/config/sparc/constraints.md
@@ -18,7 +18,7 @@
;; <http://www.gnu.org/licenses/>.
;;; Unused letters:
-;;; AB U
+;;; AB
;;; a jkl q tuv xyz
@@ -130,6 +130,15 @@
(match_code "mem")
(match_test "memory_ok_for_ldd (op)")))
+;; Not needed in 64-bit mode
+(define_constraint "U"
+ "Pseudo-register or hard even-numbered integer register"
+ (and (match_test "TARGET_ARCH32")
+ (match_code "reg")
+ (ior (match_test "REGNO (op) < FIRST_PSEUDO_REGISTER")
+ (not (match_test "reload_in_progress && reg_renumber [REGNO (op)] <
0")))
+ (match_test "register_ok_for_ldd (op)")))
+
;; Equivalent to 'T' but available in 64-bit mode
(define_memory_constraint "W"
"Memory reference for 'e' constraint floating-point register"
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 4a44078..f604f46 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -1595,9 +1595,9 @@
(define_insn "*movdi_insn_sp32"
[(set (match_operand:DI 0 "nonimmediate_operand"
-
"=T,o,T,r,o,r,r,r,?T,?*f,?*f,?o,?*e,?*e, r,?*f,?*e,?W,b,b")
+
"=T,o,T,U,o,r,r,r,?T,?*f,?*f,?o,?*e,?*e, r,?*f,?*e,?W,b,b")
(match_operand:DI 1 "input_operand"
- " J,J,r,T,r,o,i,r,*f, T, o,*f, *e,
*e,?*f, r, W,*e,J,P"))]
+ " J,J,U,T,r,o,i,r,*f, T, o,*f, *e,
*e,?*f, r, W,*e,J,P"))]
"! TARGET_ARCH64
&& (register_operand (operands[0], DImode)
|| register_or_zero_operand (operands[1], DImode))"
@@ -2302,8 +2302,8 @@
})
(define_insn "*movdf_insn_sp32"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=b,b,e,e,*r, f,
e,T,W,r,T, f, *r, o,o")
- (match_operand:DF 1 "input_operand" "G,C,e,e,
f,*r,W#F,G,e,T,r,o#F,*roF,*rG,f"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=b,b,e,e,*r, f,
e,T,W,U,T, f, *r, o,o")
+ (match_operand:DF 1 "input_operand" "G,C,e,e,
f,*r,W#F,G,e,T,U,o#F,*roF,*rG,f"))]
"! TARGET_ARCH64
&& (register_operand (operands[0], DFmode)
|| register_or_zero_or_all_ones_operand (operands[1], DFmode))"
@@ -2541,8 +2541,8 @@
})
(define_insn "*movtf_insn_sp32"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,o, o,r, r")
- (match_operand:TF 1 "input_operand" " G,oe,e,rG,o,roG"))]
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,o, o,U, r")
+ (match_operand:TF 1 "input_operand" " G,oe,e,rGU,o,roG"))]
"! TARGET_ARCH64
&& (register_operand (operands[0], TFmode)
|| register_or_zero_operand (operands[1], TFmode))"
@@ -7911,8 +7911,8 @@
(set_attr "cpu_feature" "vis,vis,vis,*,*,*,*,*,vis3,vis3,*")])
(define_insn "*mov<VM64:mode>_insn_sp32"
- [(set (match_operand:VM64 0 "nonimmediate_operand" "=e,e,e,*r, f,e,m,m,r,T,
o,*r")
- (match_operand:VM64 1 "input_operand" "Y,C,e,
f,*r,m,e,Y,T,r,*r,*r"))]
+ [(set (match_operand:VM64 0 "nonimmediate_operand" "=e,e,e,*r, f,e,m,m,U,T,
o,*r")
+ (match_operand:VM64 1 "input_operand" "Y,C,e,
f,*r,m,e,Y,T,U,*r,*r"))]
"TARGET_VIS
&& ! TARGET_ARCH64
&& (register_operand (operands[0], <VM64:MODE>mode)
diff --git a/gcc/config/sparc/sync.md b/gcc/config/sparc/sync.md
index 302cd74..d11f663 100644
--- a/gcc/config/sparc/sync.md
+++ b/gcc/config/sparc/sync.md
@@ -115,7 +115,7 @@
})
(define_insn "atomic_loaddi_1"
- [(set (match_operand:DI 0 "register_operand" "=r,?*f")
+ [(set (match_operand:DI 0 "register_operand" "=U,?*f")
(unspec:DI [(match_operand:DI 1 "memory_operand" "m,m")]
UNSPEC_ATOMIC))]
"!TARGET_ARCH64"
@@ -144,7 +144,7 @@
(define_insn "atomic_storedi_1"
[(set (match_operand:DI 0 "memory_operand" "=m,m,m")
(unspec:DI
- [(match_operand:DI 1 "register_or_v9_zero_operand" "J,r,?*f")]
+ [(match_operand:DI 1 "register_or_v9_zero_operand" "J,U,?*f")]
UNSPEC_ATOMIC))]
"!TARGET_ARCH64"
"@
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 6aa2374..68b530d 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3278,6 +3278,9 @@ instruction sequence
@item T
Memory address aligned to an 8-byte boundary
+@item U
+Even register
+
@item W
Memory address for @samp{e} constraint registers
--
1.7.12.2.dirty
