Re: [PATCH] Update {skylake,icelake,alderlake}_cost to add a bit preference to vector store.

[Hongtao Liu via Gcc-patches]

On Wed, Jun 8, 2022 at 11:44 AM Cui, Lili  wrote:
>
> > -Original Message-
> > From: Hongtao Liu 
> > Sent: Monday, June 6, 2022 1:25 PM
> > To: H.J. Lu 
> > Cc: Cui, Lili ; Liu, Hongtao ; 
> > GCC
> > Patches 
> > Subject: Re: [PATCH] Update {skylake,icelake,alderlake}_cost to add a bit
> > preference to vector store.
> > >
> > > Should we add some tests to verify improvements?
> > We can take pr99881.c as a unit test.
> >
> > Ok for the trunk.
> > >
> > > --
> > > H.J.
> >
> Hi hongtao,
>
> 1. I added test case pr105493.c for 525.x264_r. For 538.imagic_r we have 
> pr99881.c.
> 2. I changed the dg-final check in pr105638.c due to code generation changes.
>
> Bootstrapped and regtested on x86_64-linux-gnu{-m32,}. Ok for trunk?
Thanks, committed to trunk.
>
> Thanks,
> Lili.
>
> >
> > --
> > BR,
> > Hongtao



-- 
BR,
Hongtao

RE: [PATCH] Update {skylake,icelake,alderlake}_cost to add a bit preference to vector store.

[Cui, Lili via Gcc-patches]

> -Original Message-
> From: Hongtao Liu 
> Sent: Monday, June 6, 2022 1:25 PM
> To: H.J. Lu 
> Cc: Cui, Lili ; Liu, Hongtao ; GCC
> Patches 
> Subject: Re: [PATCH] Update {skylake,icelake,alderlake}_cost to add a bit
> preference to vector store.
> >
> > Should we add some tests to verify improvements?
> We can take pr99881.c as a unit test.
> 
> Ok for the trunk.
> >
> > --
> > H.J.
> 
Hi hongtao,

1. I added test case pr105493.c for 525.x264_r. For 538.imagic_r we have 
pr99881.c.
2. I changed the dg-final check in pr105638.c due to code generation changes.

Bootstrapped and regtested on x86_64-linux-gnu{-m32,}. Ok for trunk?

Thanks,
Lili.

> 
> --
> BR,
> Hongtao


0001-Update-skylake-icelake-alderlake-_cost-to-add-a-bit-.patch
Description: 0001-Update-skylake-icelake-alderlake-_cost-to-add-a-bit-.patch

Re: [PATCH] Update {skylake,icelake,alderlake}_cost to add a bit preference to vector store.

[Hongtao Liu via Gcc-patches]

On Wed, Jun 1, 2022 at 11:56 PM H.J. Lu via Gcc-patches
 wrote:
>
> On Tue, May 31, 2022 at 10:06 PM Cui,Lili  wrote:
> >
> > This patch is to update {skylake,icelake,alderlake}_cost to add a bit 
> > preference to vector store.
> > Since the interger vector construction cost has changed, we need to adjust 
> > the load and store costs for intel processers.
> >
> > With the patch applied
> > 538.imagic_r:gets ~6% improvement on ADL for multicopy.
> > 525.x264_r  :gets ~2% improvement on ADL and ICX for multicopy.
> > with no measurable changes for other benchmarks.
> >
> > Bootstrapped and regtested on x86_64-linux-gnu{-m32,}. Ok for trunk?
> >
> > Thanks,
> > Lili.
> >
> > gcc/ChangeLog
> >
> > PR target/105493
> > * config/i386/x86-tune-costs.h (skylake_cost): Raise the gpr load 
> > cost
> > from 4 to 6 and gpr store cost from 6 to 8. Change SSE loads and
> > unaligned loads cost from {6, 6, 6, 10, 20} to {8, 8, 8, 8, 16}.
> > (icelake_cost): Ditto.
> > (alderlake_cost): Raise the gpr store cost from 6 to 8 and SSE 
> > loads,
> > stores and unaligned stores cost from {6, 6, 6, 10, 15} to
> > {8, 8, 8, 10, 15}.
> >
> > gcc/testsuite/
> >
> > PR target/105493
> > * gcc.target/i386/pr91446.c: Adjust to expect vectorization
> > * gcc.target/i386/pr99881.c: XFAIL.
> > ---
> >  gcc/config/i386/x86-tune-costs.h| 26 -
> >  gcc/testsuite/gcc.target/i386/pr91446.c |  2 +-
> >  gcc/testsuite/gcc.target/i386/pr99881.c |  2 +-
> >  3 files changed, 15 insertions(+), 15 deletions(-)
> >
> > diff --git a/gcc/config/i386/x86-tune-costs.h 
> > b/gcc/config/i386/x86-tune-costs.h
> > index ea34a939c68..6c9066c84cc 100644
> > --- a/gcc/config/i386/x86-tune-costs.h
> > +++ b/gcc/config/i386/x86-tune-costs.h
> > @@ -1897,15 +1897,15 @@ struct processor_costs skylake_cost = {
> >8,   /* "large" insn */
> >17,  /* MOVE_RATIO */
> >17,  /* CLEAR_RATIO */
> > -  {4, 4, 4},   /* cost of loading integer registers
> > +  {6, 6, 6},   /* cost of loading integer registers
> >in QImode, HImode and SImode.
> >Relative to reg-reg move (2).  */
> > -  {6, 6, 6},   /* cost of storing integer 
> > registers */
> > -  {6, 6, 6, 10, 20},   /* cost of loading SSE register
> > +  {8, 8, 8},   /* cost of storing integer 
> > registers */
> > +  {8, 8, 8, 8, 16},/* cost of loading SSE register
> >in 32bit, 64bit, 128bit, 256bit 
> > and 512bit */
> >{8, 8, 8, 8, 16},/* cost of storing SSE register
> >in 32bit, 64bit, 128bit, 256bit 
> > and 512bit */
> > -  {6, 6, 6, 10, 20},   /* cost of unaligned loads.  */
> > +  {8, 8, 8, 8, 16},/* cost of unaligned loads.  */
> >{8, 8, 8, 8, 16},/* cost of unaligned stores.  */
> >2, 2, 4, /* cost of moving XMM,YMM,ZMM 
> > register */
> >6,   /* cost of moving SSE register to 
> > integer.  */
> > @@ -2023,15 +2023,15 @@ struct processor_costs icelake_cost = {
> >8,   /* "large" insn */
> >17,  /* MOVE_RATIO */
> >17,  /* CLEAR_RATIO */
> > -  {4, 4, 4},   /* cost of loading integer registers
> > +  {6, 6, 6},   /* cost of loading integer registers
> >in QImode, HImode and SImode.
> >Relative to reg-reg move (2).  */
> > -  {6, 6, 6},   /* cost of storing integer 
> > registers */
> > -  {6, 6, 6, 10, 20},   /* cost of loading SSE register
> > +  {8, 8, 8},   /* cost of storing integer 
> > registers */
> > +  {8, 8, 8, 8, 16},/* cost of loading SSE register
> >in 32bit, 64bit, 128bit, 256bit 
> > and 512bit */
> >{8, 8, 8, 8, 16},/* cost of storing SSE register
> >in 32bit, 64bit, 128bit, 256bit 
> > and 512bit */
> > -  {6, 6, 6, 10, 20},   /* cost of unaligned loads.  */
> > +  {8, 8, 8, 8, 16},/* cost of unaligned loads.  */
> >{8, 8, 8, 8, 16},/* cost of unaligned stores.  */
> >2, 2, 4, /* cost of moving XMM,YMM,ZMM 
> > register */
> >6,   /* cost of moving SSE 

Re: [PATCH] Update {skylake,icelake,alderlake}_cost to add a bit preference to vector store.

[H.J. Lu via Gcc-patches]

On Tue, May 31, 2022 at 10:06 PM Cui,Lili  wrote:
>
> This patch is to update {skylake,icelake,alderlake}_cost to add a bit 
> preference to vector store.
> Since the interger vector construction cost has changed, we need to adjust 
> the load and store costs for intel processers.
>
> With the patch applied
> 538.imagic_r:gets ~6% improvement on ADL for multicopy.
> 525.x264_r  :gets ~2% improvement on ADL and ICX for multicopy.
> with no measurable changes for other benchmarks.
>
> Bootstrapped and regtested on x86_64-linux-gnu{-m32,}. Ok for trunk?
>
> Thanks,
> Lili.
>
> gcc/ChangeLog
>
> PR target/105493
> * config/i386/x86-tune-costs.h (skylake_cost): Raise the gpr load cost
> from 4 to 6 and gpr store cost from 6 to 8. Change SSE loads and
> unaligned loads cost from {6, 6, 6, 10, 20} to {8, 8, 8, 8, 16}.
> (icelake_cost): Ditto.
> (alderlake_cost): Raise the gpr store cost from 6 to 8 and SSE loads,
> stores and unaligned stores cost from {6, 6, 6, 10, 15} to
> {8, 8, 8, 10, 15}.
>
> gcc/testsuite/
>
> PR target/105493
> * gcc.target/i386/pr91446.c: Adjust to expect vectorization
> * gcc.target/i386/pr99881.c: XFAIL.
> ---
>  gcc/config/i386/x86-tune-costs.h| 26 -
>  gcc/testsuite/gcc.target/i386/pr91446.c |  2 +-
>  gcc/testsuite/gcc.target/i386/pr99881.c |  2 +-
>  3 files changed, 15 insertions(+), 15 deletions(-)
>
> diff --git a/gcc/config/i386/x86-tune-costs.h 
> b/gcc/config/i386/x86-tune-costs.h
> index ea34a939c68..6c9066c84cc 100644
> --- a/gcc/config/i386/x86-tune-costs.h
> +++ b/gcc/config/i386/x86-tune-costs.h
> @@ -1897,15 +1897,15 @@ struct processor_costs skylake_cost = {
>8,   /* "large" insn */
>17,  /* MOVE_RATIO */
>17,  /* CLEAR_RATIO */
> -  {4, 4, 4},   /* cost of loading integer registers
> +  {6, 6, 6},   /* cost of loading integer registers
>in QImode, HImode and SImode.
>Relative to reg-reg move (2).  */
> -  {6, 6, 6},   /* cost of storing integer registers 
> */
> -  {6, 6, 6, 10, 20},   /* cost of loading SSE register
> +  {8, 8, 8},   /* cost of storing integer registers 
> */
> +  {8, 8, 8, 8, 16},/* cost of loading SSE register
>in 32bit, 64bit, 128bit, 256bit 
> and 512bit */
>{8, 8, 8, 8, 16},/* cost of storing SSE register
>in 32bit, 64bit, 128bit, 256bit 
> and 512bit */
> -  {6, 6, 6, 10, 20},   /* cost of unaligned loads.  */
> +  {8, 8, 8, 8, 16},/* cost of unaligned loads.  */
>{8, 8, 8, 8, 16},/* cost of unaligned stores.  */
>2, 2, 4, /* cost of moving XMM,YMM,ZMM 
> register */
>6,   /* cost of moving SSE register to 
> integer.  */
> @@ -2023,15 +2023,15 @@ struct processor_costs icelake_cost = {
>8,   /* "large" insn */
>17,  /* MOVE_RATIO */
>17,  /* CLEAR_RATIO */
> -  {4, 4, 4},   /* cost of loading integer registers
> +  {6, 6, 6},   /* cost of loading integer registers
>in QImode, HImode and SImode.
>Relative to reg-reg move (2).  */
> -  {6, 6, 6},   /* cost of storing integer registers 
> */
> -  {6, 6, 6, 10, 20},   /* cost of loading SSE register
> +  {8, 8, 8},   /* cost of storing integer registers 
> */
> +  {8, 8, 8, 8, 16},/* cost of loading SSE register
>in 32bit, 64bit, 128bit, 256bit 
> and 512bit */
>{8, 8, 8, 8, 16},/* cost of storing SSE register
>in 32bit, 64bit, 128bit, 256bit 
> and 512bit */
> -  {6, 6, 6, 10, 20},   /* cost of unaligned loads.  */
> +  {8, 8, 8, 8, 16},/* cost of unaligned loads.  */
>{8, 8, 8, 8, 16},/* cost of unaligned stores.  */
>2, 2, 4, /* cost of moving XMM,YMM,ZMM 
> register */
>6,   /* cost of moving SSE register to 
> integer.  */
> @@ -2146,13 +2146,13 @@ struct processor_costs alderlake_cost = {
>{6, 6, 6},   /* cost of loading integer registers
>in QImode, HImode and SImode.
>

[PATCH] Update {skylake, icelake, alderlake}_cost to add a bit preference to vector store.

[Cui,Lili via Gcc-patches]

This patch is to update {skylake,icelake,alderlake}_cost to add a bit 
preference to vector store.
Since the interger vector construction cost has changed, we need to adjust the 
load and store costs for intel processers.

With the patch applied
538.imagic_r:gets ~6% improvement on ADL for multicopy.
525.x264_r  :gets ~2% improvement on ADL and ICX for multicopy.
with no measurable changes for other benchmarks.

Bootstrapped and regtested on x86_64-linux-gnu{-m32,}. Ok for trunk?

Thanks,
Lili.

gcc/ChangeLog

PR target/105493
* config/i386/x86-tune-costs.h (skylake_cost): Raise the gpr load cost
from 4 to 6 and gpr store cost from 6 to 8. Change SSE loads and
unaligned loads cost from {6, 6, 6, 10, 20} to {8, 8, 8, 8, 16}.
(icelake_cost): Ditto.
(alderlake_cost): Raise the gpr store cost from 6 to 8 and SSE loads,
stores and unaligned stores cost from {6, 6, 6, 10, 15} to
{8, 8, 8, 10, 15}.

gcc/testsuite/

PR target/105493
* gcc.target/i386/pr91446.c: Adjust to expect vectorization
* gcc.target/i386/pr99881.c: XFAIL.
---
 gcc/config/i386/x86-tune-costs.h| 26 -
 gcc/testsuite/gcc.target/i386/pr91446.c |  2 +-
 gcc/testsuite/gcc.target/i386/pr99881.c |  2 +-
 3 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h
index ea34a939c68..6c9066c84cc 100644
--- a/gcc/config/i386/x86-tune-costs.h
+++ b/gcc/config/i386/x86-tune-costs.h
@@ -1897,15 +1897,15 @@ struct processor_costs skylake_cost = {
   8,   /* "large" insn */
   17,  /* MOVE_RATIO */
   17,  /* CLEAR_RATIO */
-  {4, 4, 4},   /* cost of loading integer registers
+  {6, 6, 6},   /* cost of loading integer registers
   in QImode, HImode and SImode.
   Relative to reg-reg move (2).  */
-  {6, 6, 6},   /* cost of storing integer registers */
-  {6, 6, 6, 10, 20},   /* cost of loading SSE register
+  {8, 8, 8},   /* cost of storing integer registers */
+  {8, 8, 8, 8, 16},/* cost of loading SSE register
   in 32bit, 64bit, 128bit, 256bit and 
512bit */
   {8, 8, 8, 8, 16},/* cost of storing SSE register
   in 32bit, 64bit, 128bit, 256bit and 
512bit */
-  {6, 6, 6, 10, 20},   /* cost of unaligned loads.  */
+  {8, 8, 8, 8, 16},/* cost of unaligned loads.  */
   {8, 8, 8, 8, 16},/* cost of unaligned stores.  */
   2, 2, 4, /* cost of moving XMM,YMM,ZMM register 
*/
   6,   /* cost of moving SSE register to 
integer.  */
@@ -2023,15 +2023,15 @@ struct processor_costs icelake_cost = {
   8,   /* "large" insn */
   17,  /* MOVE_RATIO */
   17,  /* CLEAR_RATIO */
-  {4, 4, 4},   /* cost of loading integer registers
+  {6, 6, 6},   /* cost of loading integer registers
   in QImode, HImode and SImode.
   Relative to reg-reg move (2).  */
-  {6, 6, 6},   /* cost of storing integer registers */
-  {6, 6, 6, 10, 20},   /* cost of loading SSE register
+  {8, 8, 8},   /* cost of storing integer registers */
+  {8, 8, 8, 8, 16},/* cost of loading SSE register
   in 32bit, 64bit, 128bit, 256bit and 
512bit */
   {8, 8, 8, 8, 16},/* cost of storing SSE register
   in 32bit, 64bit, 128bit, 256bit and 
512bit */
-  {6, 6, 6, 10, 20},   /* cost of unaligned loads.  */
+  {8, 8, 8, 8, 16},/* cost of unaligned loads.  */
   {8, 8, 8, 8, 16},/* cost of unaligned stores.  */
   2, 2, 4, /* cost of moving XMM,YMM,ZMM register 
*/
   6,   /* cost of moving SSE register to 
integer.  */
@@ -2146,13 +2146,13 @@ struct processor_costs alderlake_cost = {
   {6, 6, 6},   /* cost of loading integer registers
   in QImode, HImode and SImode.
   Relative to reg-reg move (2).  */
-  {6, 6, 6},   /* cost of storing integer registers */
-  {6, 6, 6, 10, 15},   /* cost of loading SSE register
+  {8, 8, 8},