Re: [PATCH 09/10] arm testsuite: XFAIL or relax registers in some tests
On 28/04/2023 17:54, Kyrylo Tkachov wrote: -Original Message- From: Andrea Corallo Sent: Friday, April 28, 2023 12:30 PM To: gcc-patches@gcc.gnu.org Cc: Kyrylo Tkachov ; Richard Earnshaw ; Stam Markianos-Wright Subject: [PATCH 09/10] arm testsuite: XFAIL or relax registers in some tests From: Stam Markianos-Wright Hi all, This is a simple testsuite tidy-up patch, addressing to types of errors: * The vcmp vector-scalar tests failing due to the compiler's preference of vector-vector comparisons, over vector-scalar comparisons. This is due to the lack of cost model for MVE and the compiler not knowing that the RTL vec_duplicate is free in those instructions. For now, we simply XFAIL these checks. I'd like to see this deficiency tracked in Bugzilla before we mark these as XFAIL. Yep! Raised https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109697 (And I'll also update this commit message to reference that PR now) * The tests for pr108177 had strict usage of q0 and r0 registers, meaning that they would FAIL with -mfloat-abi=softf. The register checks have now been relaxed. This part is ok. Thanks, Kyrill gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/srshr.c: XFAIL check. * gcc.target/arm/mve/intrinsics/srshrl.c: XFAIL check. * gcc.target/arm/mve/intrinsics/uqshl.c: XFAIL check. * gcc.target/arm/mve/intrinsics/uqshll.c: XFAIL check. * gcc.target/arm/mve/intrinsics/urshr.c: XFAIL check. * gcc.target/arm/mve/intrinsics/urshrl.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadciq_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadciq_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadcq_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadcq_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbciq_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbciq_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbcq_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbcq_u32.c: XFAIL check. * gcc.target/arm/mve/pr108177-1.c: Relax registers. * gcc.target/arm/mve/pr108177-10.c: Relax registers. * gcc.target/arm/mve/pr108177-11.c: Relax registers. * gcc.target/arm/mve/pr108177-12.c: Relax registers. * gcc.target/arm/mve/pr108177-13.c: Relax registers. * gcc.target/arm/mve/pr108177-14.c: Relax registers. * gcc.target/arm/mve/pr108177-2.c: Relax registers. * gcc.target/arm/mve/pr108177-3.c: Relax registers. * gcc.target/arm/mve/pr108177-4.c: Relax registers. * gcc.target/arm/mve/pr108177-5.c: Relax registers. * gcc.target/arm/mve/pr108177-6.c: Relax registers. * gcc.target/arm/mve/pr108177-7.c: Relax registers. * gcc.target/arm/mve/pr108177-8.c: Relax registers. * gcc.target/arm/mve/pr108177-9.c: Relax registers. --- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c | 2 +- gcc/testsuite/gcc.target/arm/mve
[PATCH 09/10] arm testsuite: XFAIL or relax registers in some tests
On 02/05/2023 09:28, Christophe Lyon wrote: Hi Stam! On 4/28/23 13:30, Andrea Corallo via Gcc-patches wrote: From: Stam Markianos-Wright Hi all, This is a simple testsuite tidy-up patch, addressing to types of errors: * The vcmp vector-scalar tests failing due to the compiler's preference of vector-vector comparisons, over vector-scalar comparisons. This is due to the lack of cost model for MVE and the compiler not knowing that the RTL vec_duplicate is free in those instructions. For now, we simply XFAIL these checks. * The tests for pr108177 had strict usage of q0 and r0 registers, meaning that they would FAIL with -mfloat-abi=softf. The register checks Very minor typo: should be "softfp" :-) Ahh indeed, thanks! Will change this before pushing Thanks, Christophe have now been relaxed. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/srshr.c: XFAIL check. * gcc.target/arm/mve/intrinsics/srshrl.c: XFAIL check. * gcc.target/arm/mve/intrinsics/uqshl.c: XFAIL check. * gcc.target/arm/mve/intrinsics/uqshll.c: XFAIL check. * gcc.target/arm/mve/intrinsics/urshr.c: XFAIL check. * gcc.target/arm/mve/intrinsics/urshrl.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadciq_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadciq_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadcq_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadcq_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbciq_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbciq_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbcq_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbcq_u32.c: XFAIL check. * gcc.target/arm/mve/pr108177-1.c: Relax registers. * gcc.target/arm/mve/pr108177-10.c: Relax registers. * gcc.target/arm/mve/pr108177-11.c: Relax registers. * gcc.target/arm/mve/pr108177-12.c: Relax registers. * gcc.target/arm/mve/pr108177-13.c: Relax registers. * gcc.target/arm/mve/pr108177-14.c: Relax registers. * gcc.target/arm/mve/pr108177-2.c: Relax registers. * gcc.target/arm/mve/pr108177-3.c: Relax registers. * gcc.target/arm/mve/pr108177-4.c: Relax registers. * gcc.target/arm/mve/pr108177-5.c: Relax registers. * gcc.target/arm/mve/pr108177-6.c: Relax registers. * gcc.target/arm/mve/pr108177-7.c: Relax registers. * gcc.target/arm/mve/pr108177-8.c: Relax registers. * gcc.target/arm/mve/pr108177-9.c: Relax registers. --- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c | 2 +- gcc/testsuite/gcc.target/arm/mve/pr108177-1.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-10.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-11.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-12.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-13.c
Re: [PATCH 09/10] arm testsuite: XFAIL or relax registers in some tests
Hi Stam! On 4/28/23 13:30, Andrea Corallo via Gcc-patches wrote: From: Stam Markianos-Wright Hi all, This is a simple testsuite tidy-up patch, addressing to types of errors: * The vcmp vector-scalar tests failing due to the compiler's preference of vector-vector comparisons, over vector-scalar comparisons. This is due to the lack of cost model for MVE and the compiler not knowing that the RTL vec_duplicate is free in those instructions. For now, we simply XFAIL these checks. * The tests for pr108177 had strict usage of q0 and r0 registers, meaning that they would FAIL with -mfloat-abi=softf. The register checks Very minor typo: should be "softfp" :-) Thanks, Christophe have now been relaxed. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/srshr.c: XFAIL check. * gcc.target/arm/mve/intrinsics/srshrl.c: XFAIL check. * gcc.target/arm/mve/intrinsics/uqshl.c: XFAIL check. * gcc.target/arm/mve/intrinsics/uqshll.c: XFAIL check. * gcc.target/arm/mve/intrinsics/urshr.c: XFAIL check. * gcc.target/arm/mve/intrinsics/urshrl.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadciq_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadciq_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadcq_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadcq_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbciq_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbciq_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbcq_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbcq_u32.c: XFAIL check. * gcc.target/arm/mve/pr108177-1.c: Relax registers. * gcc.target/arm/mve/pr108177-10.c: Relax registers. * gcc.target/arm/mve/pr108177-11.c: Relax registers. * gcc.target/arm/mve/pr108177-12.c: Relax registers. * gcc.target/arm/mve/pr108177-13.c: Relax registers. * gcc.target/arm/mve/pr108177-14.c: Relax registers. * gcc.target/arm/mve/pr108177-2.c: Relax registers. * gcc.target/arm/mve/pr108177-3.c: Relax registers. * gcc.target/arm/mve/pr108177-4.c: Relax registers. * gcc.target/arm/mve/pr108177-5.c: Relax registers. * gcc.target/arm/mve/pr108177-6.c: Relax registers. * gcc.target/arm/mve/pr108177-7.c: Relax registers. * gcc.target/arm/mve/pr108177-8.c: Relax registers. * gcc.target/arm/mve/pr108177-9.c: Relax registers. --- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c | 2 +- gcc/testsuite/gcc.target/arm/mve/pr108177-1.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-10.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-11.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-12.c | 4 ++--
RE: [PATCH 09/10] arm testsuite: XFAIL or relax registers in some tests
> -Original Message- > From: Andrea Corallo > Sent: Friday, April 28, 2023 12:30 PM > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov ; Richard Earnshaw > ; Stam Markianos-Wright wri...@arm.com> > Subject: [PATCH 09/10] arm testsuite: XFAIL or relax registers in some tests > > From: Stam Markianos-Wright > > Hi all, > > This is a simple testsuite tidy-up patch, addressing to types of errors: > > * The vcmp vector-scalar tests failing due to the compiler's preference > of vector-vector comparisons, over vector-scalar comparisons. This is > due to the lack of cost model for MVE and the compiler not knowing that > the RTL vec_duplicate is free in those instructions. For now, we simply > XFAIL these checks. I'd like to see this deficiency tracked in Bugzilla before we mark these as XFAIL. > * The tests for pr108177 had strict usage of q0 and r0 registers, > meaning that they would FAIL with -mfloat-abi=softf. The register checks > have now been relaxed. This part is ok. Thanks, Kyrill > > gcc/testsuite/ChangeLog: > > * gcc.target/arm/mve/intrinsics/srshr.c: XFAIL check. > * gcc.target/arm/mve/intrinsics/srshrl.c: XFAIL check. > * gcc.target/arm/mve/intrinsics/uqshl.c: XFAIL check. > * gcc.target/arm/mve/intrinsics/uqshll.c: XFAIL check. > * gcc.target/arm/mve/intrinsics/urshr.c: XFAIL check. > * gcc.target/arm/mve/intrinsics/urshrl.c: XFAIL check. > * gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: XFAIL check. > * gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: XFAIL check. > * gcc.target/arm/mve/intrinsics/vadciq_s32.c: XFAIL check. > * gcc.target/arm/mve/intrinsics/vadciq_u32.c: XFAIL check. > * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: XFAIL check. > * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: XFAIL check. > * gcc.target/arm/mve/intrinsics/vadcq_s32.c: XFAIL check. > * gcc.target/arm/mve/intrinsics/vadcq_u32.c: XFAIL check. > * gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: XFAIL check. > * gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: XFAIL check. > * gcc.target/arm/mve/intrinsics/vsbciq_s32.c: XFAIL check. > * gcc.target/arm/mve/intrinsics/vsbciq_u32.c: XFAIL check. > * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: XFAIL check. > * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: XFAIL check. > * gcc.target/arm/mve/intrinsics/vsbcq_s32.c: XFAIL check. > * gcc.target/arm/mve/intrinsics/vsbcq_u32.c: XFAIL check. > * gcc.target/arm/mve/pr108177-1.c: Relax registers. > * gcc.target/arm/mve/pr108177-10.c: Relax registers. > * gcc.target/arm/mve/pr108177-11.c: Relax registers. > * gcc.target/arm/mve/pr108177-12.c: Relax registers. > * gcc.target/arm/mve/pr108177-13.c: Relax registers. > * gcc.target/arm/mve/pr108177-14.c: Relax registers. > * gcc.target/arm/mve/pr108177-2.c: Relax registers. > * gcc.target/arm/mve/pr108177-3.c: Relax registers. > * gcc.target/arm/mve/pr108177-4.c: Relax registers. > * gcc.target/arm/mve/pr108177-5.c: Relax registers. > * gcc.target/arm/mve/pr108177-6.c: Relax registers. > * gcc.target/arm/mve/pr108177-7.c: Relax registers. > * gcc.target/arm/mve/pr108177-8.c: Relax registers. > * gcc.target/arm/mve/pr108177-9.c: Relax registers. > --- > gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c | 2 +- > gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c | 2 +- > gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c | 2 +- > gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c | 2 +- > gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c | 2 +- > gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c | 2 +- > gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c | 2 +- > gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c | 2 +- > gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c | 2 +- > gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c | 2 +- > gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c | 2 +- > gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c | 2 +- > gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c | 2 +- > gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c | 2 +- > gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c | 2 +- > gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c | 2 +- > gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c | 2 +- > gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 2 +- > gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 2 +- > gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f
[PATCH 09/10] arm testsuite: XFAIL or relax registers in some tests
From: Stam Markianos-Wright Hi all, This is a simple testsuite tidy-up patch, addressing to types of errors: * The vcmp vector-scalar tests failing due to the compiler's preference of vector-vector comparisons, over vector-scalar comparisons. This is due to the lack of cost model for MVE and the compiler not knowing that the RTL vec_duplicate is free in those instructions. For now, we simply XFAIL these checks. * The tests for pr108177 had strict usage of q0 and r0 registers, meaning that they would FAIL with -mfloat-abi=softf. The register checks have now been relaxed. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/srshr.c: XFAIL check. * gcc.target/arm/mve/intrinsics/srshrl.c: XFAIL check. * gcc.target/arm/mve/intrinsics/uqshl.c: XFAIL check. * gcc.target/arm/mve/intrinsics/uqshll.c: XFAIL check. * gcc.target/arm/mve/intrinsics/urshr.c: XFAIL check. * gcc.target/arm/mve/intrinsics/urshrl.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadciq_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadciq_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadcq_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vadcq_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbciq_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbciq_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbcq_s32.c: XFAIL check. * gcc.target/arm/mve/intrinsics/vsbcq_u32.c: XFAIL check. * gcc.target/arm/mve/pr108177-1.c: Relax registers. * gcc.target/arm/mve/pr108177-10.c: Relax registers. * gcc.target/arm/mve/pr108177-11.c: Relax registers. * gcc.target/arm/mve/pr108177-12.c: Relax registers. * gcc.target/arm/mve/pr108177-13.c: Relax registers. * gcc.target/arm/mve/pr108177-14.c: Relax registers. * gcc.target/arm/mve/pr108177-2.c: Relax registers. * gcc.target/arm/mve/pr108177-3.c: Relax registers. * gcc.target/arm/mve/pr108177-4.c: Relax registers. * gcc.target/arm/mve/pr108177-5.c: Relax registers. * gcc.target/arm/mve/pr108177-6.c: Relax registers. * gcc.target/arm/mve/pr108177-7.c: Relax registers. * gcc.target/arm/mve/pr108177-8.c: Relax registers. * gcc.target/arm/mve/pr108177-9.c: Relax registers. --- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c | 2 +- gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c | 2 +- gcc/testsuite/gcc.target/arm/mve/pr108177-1.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-10.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-11.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-12.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-13.c | 4 ++-- gcc/testsuite/gcc.target/arm/mve/pr108177-14.c | 4 ++--
