Re: [PATCH 1/2] Core definition for APM XGene-1 and associated cost-table.

2014-12-05 Thread Marcus Shawcroft 
On 21 November 2014 at 18:44, Philipp Tomsich
philipp.toms...@theobroma-systems.com wrote:

 +2014-11-19  Philipp Tomsich  philipp.toms...@theobroma-systems.com
 +
 +   * config/aarch64/aarch64-cores.def (xgene1): Update/add the
 +   xgene1 (APM XGene-1) core definition.
 +   * gcc/config/aarch64/aarch64.c: Add cost tables for APM XGene-1
 +   * config/arm/aarch-cost-tables.h: Add cost tables for APM XGene-1
 +   * doc/invoke.texi: Document -mcpu=xgene1.


OK provide the comments in Ramana's earlier response have been addressed.
/Marcus

Re: [PATCH 1/2] Core definition for APM XGene-1 and associated cost-table.

2014-12-02 Thread Ramana Radhakrishnan 
On Fri, Nov 21, 2014 at 6:44 PM, Philipp Tomsich
philipp.toms...@theobroma-systems.com wrote:
 To keep this change separately buildable from the pipeline model,
 this patch directs the APM XGene-1 to use the generic scheduling
 model.
 ---
  gcc/ChangeLog|   8 +++
  gcc/config/aarch64/aarch64-cores.def |   1 +
  gcc/config/aarch64/aarch64-tune.md   |   2 +-
  gcc/config/aarch64/aarch64.c |  62 +
  gcc/config/arm/aarch-cost-tables.h   | 101 
 +++
  gcc/doc/invoke.texi  |   3 +-
  6 files changed, 175 insertions(+), 2 deletions(-)

 diff --git a/gcc/ChangeLog b/gcc/ChangeLog
 index 2fa58ca..c9ac0d9 100644
 --- a/gcc/ChangeLog
 +++ b/gcc/ChangeLog
 @@ -1,3 +1,11 @@
 +2014-11-19  Philipp Tomsich  philipp.toms...@theobroma-systems.com
 +
 +   * config/aarch64/aarch64-cores.def (xgene1): Update/add the
 +   xgene1 (APM XGene-1) core definition.
 +   * gcc/config/aarch64/aarch64.c: Add cost tables for APM XGene-1
 +   * config/arm/aarch-cost-tables.h: Add cost tables for APM XGene-1
 +   * doc/invoke.texi: Document -mcpu=xgene1.

Changes to config/arm/ files are ok as long as you've built a
cross-compiler for arm-none-eabi and ensured that a build succeeds.

regards
Ramana

 +
  2014-11-18  Maciej W. Rozycki  ma...@codesourcery.com

 * config/mips/mips.md (compression): Add `micromips32' setting.
 diff --git a/gcc/config/aarch64/aarch64-cores.def 
 b/gcc/config/aarch64/aarch64-cores.def
 index 312941f..e553e50 100644
 --- a/gcc/config/aarch64/aarch64-cores.def
 +++ b/gcc/config/aarch64/aarch64-cores.def
 @@ -37,6 +37,7 @@
  AARCH64_CORE(cortex-a53,  cortexa53, cortexa53, 8,  AARCH64_FL_FPSIMD | 
 AARCH64_FL_CRC, cortexa53)
  AARCH64_CORE(cortex-a57,  cortexa15, cortexa15, 8,  AARCH64_FL_FPSIMD | 
 AARCH64_FL_CRC, cortexa57)
  AARCH64_CORE(thunderx,thunderx,  thunderx, 8,  AARCH64_FL_FPSIMD | 
 AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx)
 +AARCH64_CORE(xgene1,  xgene1,xgene1,8,  AARCH64_FL_FPSIMD, 
 xgene1)

  /* V8 big.LITTLE implementations.  */

 diff --git a/gcc/config/aarch64/aarch64-tune.md 
 b/gcc/config/aarch64/aarch64-tune.md
 index c717ea8..6409082 100644
 --- a/gcc/config/aarch64/aarch64-tune.md
 +++ b/gcc/config/aarch64/aarch64-tune.md
 @@ -1,5 +1,5 @@
  ;; -*- buffer-read-only: t -*-
  ;; Generated automatically by gentune.sh from aarch64-cores.def
  (define_attr tune
 -   cortexa53,cortexa15,thunderx,cortexa57cortexa53
 +   cortexa53,cortexa15,thunderx,xgene1,cortexa57cortexa53
 (const (symbol_ref ((enum attr_tune) aarch64_tune
 diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
 index 4fec21e..9b92527 100644
 --- a/gcc/config/aarch64/aarch64.c
 +++ b/gcc/config/aarch64/aarch64.c
 @@ -226,6 +226,27 @@ static const struct cpu_addrcost_table 
 cortexa57_addrcost_table =
  #if HAVE_DESIGNATED_INITIALIZERS  GCC_VERSION = 2007
  __extension__
  #endif
 +static const struct cpu_addrcost_table xgene1_addrcost_table =
 +{
 +#if HAVE_DESIGNATED_INITIALIZERS
 +  .addr_scale_costs =
 +#endif
 +{
 +  NAMED_PARAM (hi, 1),
 +  NAMED_PARAM (si, 0),
 +  NAMED_PARAM (di, 0),
 +  NAMED_PARAM (ti, 1),
 +},
 +  NAMED_PARAM (pre_modify, 1),
 +  NAMED_PARAM (post_modify, 0),
 +  NAMED_PARAM (register_offset, 0),
 +  NAMED_PARAM (register_extend, 1),
 +  NAMED_PARAM (imm_offset, 0),
 +};
 +
 +#if HAVE_DESIGNATED_INITIALIZERS  GCC_VERSION = 2007
 +__extension__
 +#endif
  static const struct cpu_regmove_cost generic_regmove_cost =
  {
NAMED_PARAM (GP2GP, 1),
 @@ -262,6 +283,17 @@ static const struct cpu_regmove_cost 
 thunderx_regmove_cost =
NAMED_PARAM (FP2FP, 4)
  };

 +static const struct cpu_regmove_cost xgene1_regmove_cost =
 +{
 +  NAMED_PARAM (GP2GP, 1),
 +  NAMED_PARAM (GP2FP, 8),
 +  NAMED_PARAM (FP2GP, 8),
 +  /* We currently do not provide direct support for TFmode Q-Q move.
 + Therefore we need to raise the cost above 2 in order to have
 + reload handle the situation.  */
 +  NAMED_PARAM (FP2FP, 4)
 +};
 +
  /* Generic costs for vector insn classes.  */
  #if HAVE_DESIGNATED_INITIALIZERS  GCC_VERSION = 2007
  __extension__
 @@ -302,6 +334,26 @@ static const struct cpu_vector_cost 
 cortexa57_vector_cost =
NAMED_PARAM (cond_not_taken_branch_cost, 1)
  };

 +/* Generic costs for vector insn classes.  */
 +#if HAVE_DESIGNATED_INITIALIZERS  GCC_VERSION = 2007
 +__extension__
 +#endif
 +static const struct cpu_vector_cost xgene1_vector_cost =
 +{
 +  NAMED_PARAM (scalar_stmt_cost, 1),
 +  NAMED_PARAM (scalar_load_cost, 5),
 +  NAMED_PARAM (scalar_store_cost, 1),
 +  NAMED_PARAM (vec_stmt_cost, 2),
 +  NAMED_PARAM (vec_to_scalar_cost, 4),
 +  NAMED_PARAM (scalar_to_vec_cost, 4),
 +  NAMED_PARAM (vec_align_load_cost, 10),
 +  NAMED_PARAM (vec_unalign_load_cost, 10),
 +  NAMED_PARAM (vec_unalign_store_cost, 2),
 +  NAMED_PARAM (vec_store_cost, 2),
 +  NAMED_PARAM (cond_taken_branch_cost, 2),

[PATCH 1/2] Core definition for APM XGene-1 and associated cost-table.

2014-11-21 Thread Philipp Tomsich 
To keep this change separately buildable from the pipeline model,
this patch directs the APM XGene-1 to use the generic scheduling
model.
---
 gcc/ChangeLog|   8 +++
 gcc/config/aarch64/aarch64-cores.def |   1 +
 gcc/config/aarch64/aarch64-tune.md   |   2 +-
 gcc/config/aarch64/aarch64.c |  62 +
 gcc/config/arm/aarch-cost-tables.h   | 101 +++
 gcc/doc/invoke.texi  |   3 +-
 6 files changed, 175 insertions(+), 2 deletions(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2fa58ca..c9ac0d9 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2014-11-19  Philipp Tomsich  philipp.toms...@theobroma-systems.com
+
+   * config/aarch64/aarch64-cores.def (xgene1): Update/add the
+   xgene1 (APM XGene-1) core definition.
+   * gcc/config/aarch64/aarch64.c: Add cost tables for APM XGene-1
+   * config/arm/aarch-cost-tables.h: Add cost tables for APM XGene-1
+   * doc/invoke.texi: Document -mcpu=xgene1.
+
 2014-11-18  Maciej W. Rozycki  ma...@codesourcery.com
 
* config/mips/mips.md (compression): Add `micromips32' setting.
diff --git a/gcc/config/aarch64/aarch64-cores.def 
b/gcc/config/aarch64/aarch64-cores.def
index 312941f..e553e50 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -37,6 +37,7 @@
 AARCH64_CORE(cortex-a53,  cortexa53, cortexa53, 8,  AARCH64_FL_FPSIMD | 
AARCH64_FL_CRC, cortexa53)
 AARCH64_CORE(cortex-a57,  cortexa15, cortexa15, 8,  AARCH64_FL_FPSIMD | 
AARCH64_FL_CRC, cortexa57)
 AARCH64_CORE(thunderx,thunderx,  thunderx, 8,  AARCH64_FL_FPSIMD | 
AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx)
+AARCH64_CORE(xgene1,  xgene1,xgene1,8,  AARCH64_FL_FPSIMD, 
xgene1)
 
 /* V8 big.LITTLE implementations.  */
 
diff --git a/gcc/config/aarch64/aarch64-tune.md 
b/gcc/config/aarch64/aarch64-tune.md
index c717ea8..6409082 100644
--- a/gcc/config/aarch64/aarch64-tune.md
+++ b/gcc/config/aarch64/aarch64-tune.md
@@ -1,5 +1,5 @@
 ;; -*- buffer-read-only: t -*-
 ;; Generated automatically by gentune.sh from aarch64-cores.def
 (define_attr tune
-   cortexa53,cortexa15,thunderx,cortexa57cortexa53
+   cortexa53,cortexa15,thunderx,xgene1,cortexa57cortexa53
(const (symbol_ref ((enum attr_tune) aarch64_tune
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 4fec21e..9b92527 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -226,6 +226,27 @@ static const struct cpu_addrcost_table 
cortexa57_addrcost_table =
 #if HAVE_DESIGNATED_INITIALIZERS  GCC_VERSION = 2007
 __extension__
 #endif
+static const struct cpu_addrcost_table xgene1_addrcost_table =
+{
+#if HAVE_DESIGNATED_INITIALIZERS
+  .addr_scale_costs =
+#endif
+{
+  NAMED_PARAM (hi, 1),
+  NAMED_PARAM (si, 0),
+  NAMED_PARAM (di, 0),
+  NAMED_PARAM (ti, 1),
+},
+  NAMED_PARAM (pre_modify, 1),
+  NAMED_PARAM (post_modify, 0),
+  NAMED_PARAM (register_offset, 0),
+  NAMED_PARAM (register_extend, 1),
+  NAMED_PARAM (imm_offset, 0),
+};
+
+#if HAVE_DESIGNATED_INITIALIZERS  GCC_VERSION = 2007
+__extension__
+#endif
 static const struct cpu_regmove_cost generic_regmove_cost =
 {
   NAMED_PARAM (GP2GP, 1),
@@ -262,6 +283,17 @@ static const struct cpu_regmove_cost thunderx_regmove_cost 
=
   NAMED_PARAM (FP2FP, 4)
 };
 
+static const struct cpu_regmove_cost xgene1_regmove_cost =
+{
+  NAMED_PARAM (GP2GP, 1),
+  NAMED_PARAM (GP2FP, 8),
+  NAMED_PARAM (FP2GP, 8),
+  /* We currently do not provide direct support for TFmode Q-Q move.
+ Therefore we need to raise the cost above 2 in order to have
+ reload handle the situation.  */
+  NAMED_PARAM (FP2FP, 4)
+};
+
 /* Generic costs for vector insn classes.  */
 #if HAVE_DESIGNATED_INITIALIZERS  GCC_VERSION = 2007
 __extension__
@@ -302,6 +334,26 @@ static const struct cpu_vector_cost cortexa57_vector_cost =
   NAMED_PARAM (cond_not_taken_branch_cost, 1)
 };
 
+/* Generic costs for vector insn classes.  */
+#if HAVE_DESIGNATED_INITIALIZERS  GCC_VERSION = 2007
+__extension__
+#endif
+static const struct cpu_vector_cost xgene1_vector_cost =
+{
+  NAMED_PARAM (scalar_stmt_cost, 1),
+  NAMED_PARAM (scalar_load_cost, 5),
+  NAMED_PARAM (scalar_store_cost, 1),
+  NAMED_PARAM (vec_stmt_cost, 2),
+  NAMED_PARAM (vec_to_scalar_cost, 4),
+  NAMED_PARAM (scalar_to_vec_cost, 4),
+  NAMED_PARAM (vec_align_load_cost, 10),
+  NAMED_PARAM (vec_unalign_load_cost, 10),
+  NAMED_PARAM (vec_unalign_store_cost, 2),
+  NAMED_PARAM (vec_store_cost, 2),
+  NAMED_PARAM (cond_taken_branch_cost, 2),
+  NAMED_PARAM (cond_not_taken_branch_cost, 1)
+};
+
 #if HAVE_DESIGNATED_INITIALIZERS  GCC_VERSION = 2007
 __extension__
 #endif
@@ -345,6 +397,16 @@ static const struct tune_params thunderx_tunings =
   NAMED_PARAM (issue_rate, 2)
 };
 
+static const struct tune_params xgene1_tunings =
+{
+  xgene1_extra_costs,
+  xgene1_addrcost_table,
+  xgene1_regmove_cost,