Re: [PATCH 1/4] RISC-V: Adjust expand_cond_len_{unary,binop,op} api

2023-09-01 Thread Lehua Ding 

On 2023/9/1 18:00, Robin Dapp via Gcc-patches wrote:

Thanks, LGTM.


Thanks, committed these patches.


Btw. I haven't forgotten to respond to your last refactor but just didn't find
the time yet.  I figured I should have some proper draft before suggesting
more things :)


Well, let's talk about it when you're free. Thanks in advance for more 
comments and suggestions later.


--
Best,
Lehua

Re: [PATCH 1/4] RISC-V: Adjust expand_cond_len_{unary,binop,op} api

2023-09-01 Thread Robin Dapp via Gcc-patches 
Thanks, LGTM.

Btw. I haven't forgotten to respond to your last refactor but just didn't find
the time yet.  I figured I should have some proper draft before suggesting
more things :)

Regards
 Robin

[PATCH 1/4] RISC-V: Adjust expand_cond_len_{unary,binop,op} api

2023-08-31 Thread Lehua Ding 
This patch change expand_cond_len_{unary,binop}'s argument `rtx_code code`
to `unsigned icode` and use the icode directly to determine whether the
rounding_mode operand is required.

gcc/ChangeLog:

* config/riscv/autovec.md: Adjust.
* config/riscv/riscv-protos.h (expand_cond_len_unop): Ditto.
(expand_cond_len_binop): Ditto.
* config/riscv/riscv-v.cc (needs_fp_rounding): Ditto.
(expand_cond_len_op): Ditto.
(expand_cond_len_unop): Ditto.
(expand_cond_len_binop): Ditto.
(expand_cond_len_ternop): Ditto.

---
 gcc/config/riscv/autovec.md | 18 +++--
 gcc/config/riscv/riscv-protos.h |  4 ++--
 gcc/config/riscv/riscv-v.cc | 34 +++--
 3 files changed, 34 insertions(+), 22 deletions(-)

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index ebe1b10aa12..006e174ebd5 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1551,7 +1551,8 @@
(match_operand 5 "const_0_operand")]
   "TARGET_VECTOR"
 {
-  riscv_vector::expand_cond_len_unop (, operands);
+  insn_code icode = code_for_pred (, mode);
+  riscv_vector::expand_cond_len_unop (icode, operands);
   DONE;
 })
 
@@ -1588,7 +1589,8 @@
(match_operand 5 "const_0_operand")]
   "TARGET_VECTOR"
 {
-  riscv_vector::expand_cond_len_unop (, operands);
+  insn_code icode = code_for_pred (, mode);
+  riscv_vector::expand_cond_len_unop (icode, operands);
   DONE;
 })
 
@@ -1627,7 +1629,8 @@
(match_operand 6 "const_0_operand")]
   "TARGET_VECTOR"
 {
-  riscv_vector::expand_cond_len_binop (, operands);
+  insn_code icode = code_for_pred (, mode);
+  riscv_vector::expand_cond_len_binop (icode, operands);
   DONE;
 })
 
@@ -1667,7 +1670,8 @@
(match_operand 6 "const_0_operand")]
   "TARGET_VECTOR"
 {
-  riscv_vector::expand_cond_len_binop (, operands);
+  insn_code icode = code_for_pred (, mode);
+  riscv_vector::expand_cond_len_binop (icode, operands);
   DONE;
 })
 
@@ -1707,7 +1711,8 @@
(match_operand 6 "const_0_operand")]
   "TARGET_VECTOR"
 {
-  riscv_vector::expand_cond_len_binop (, operands);
+  insn_code icode = code_for_pred (, mode);
+  riscv_vector::expand_cond_len_binop (icode, operands);
   DONE;
 })
 
@@ -1745,7 +1750,8 @@
(match_operand 6 "const_0_operand")]
   "TARGET_VECTOR"
 {
-  riscv_vector::expand_cond_len_binop (, operands);
+  insn_code icode = code_for_pred (, mode);
+  riscv_vector::expand_cond_len_binop (icode, operands);
   DONE;
 })
 
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index e145ee6c69b..dd7aa360ec5 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -426,8 +426,8 @@ bool neg_simm5_p (rtx);
 bool has_vi_variant_p (rtx_code, rtx);
 void expand_vec_cmp (rtx, rtx_code, rtx, rtx);
 bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool);
-void expand_cond_len_unop (rtx_code, rtx *);
-void expand_cond_len_binop (rtx_code, rtx *);
+void expand_cond_len_unop (unsigned, rtx *);
+void expand_cond_len_binop (unsigned, rtx *);
 void expand_reduction (rtx_code, rtx *, rtx,
   reduction_type = reduction_type::UNORDERED);
 #endif
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 6228ff3d92e..89ac4743f40 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -245,6 +245,12 @@ public:
   always Pmode.  */
if (mode == VOIDmode)
  mode = Pmode;
+   else
+ /* Early assertion ensures same mode since maybe_legitimize_operand
+will check this.  */
+ gcc_assert (GET_MODE (ops[opno]) == VOIDmode
+ || GET_MODE (ops[opno]) == mode);
+
add_input_operand (ops[opno], mode);
   }
 
@@ -291,6 +297,7 @@ public:
 if (m_insn_flags & FRM_DYN_P)
   add_rounding_mode_operand (FRM_DYN);
 
+gcc_assert (insn_data[(int) icode].n_operands == m_opno);
 expand (icode, any_mem_p);
   }
 
@@ -2951,17 +2958,20 @@ expand_load_store (rtx *ops, bool is_load)
 
 /* Return true if the operation is the floating-point operation need FRM.  */
 static bool
-needs_fp_rounding (rtx_code code, machine_mode mode)
+needs_fp_rounding (unsigned icode, machine_mode mode)
 {
   if (!FLOAT_MODE_P (mode))
 return false;
-  return code != SMIN && code != SMAX && code != NEG && code != ABS;
+
+  return icode != maybe_code_for_pred (SMIN, mode)
+&& icode != maybe_code_for_pred (SMAX, mode)
+&& icode != maybe_code_for_pred (NEG, mode)
+&& icode != maybe_code_for_pred (ABS, mode);
 }
 
 /* Subroutine to expand COND_LEN_* patterns.  */
 static void
-expand_cond_len_op (rtx_code code, unsigned icode, insn_flags op_type, rtx 
*ops,
-   rtx len)
+expand_cond_len_op (unsigned icode, insn_flags op_type, rtx *ops, rtx len)
 {
   rtx dest = ops[0];
   rtx mask = ops[1];
@@ -2980,7 +2990,7 @@ expand_cond_len_op (rtx_code code, unsigned icode, 
insn_flags op_type, r