Re: [PATCH 2/3][AArch64 nofp] Clarify docs for +nofp/-mgeneral-regs-only
On Tue, Jun 23, 2015 at 05:03:13PM +0100, Alan Lawrence wrote:
James Greenhalgh wrote:
snip
To my eye, beginning a sentence in lowercase looks very odd in pdf, and still
a
bit odd in html. Have changed to That is...?
Tested with make pdf make html.
gcc/ChangeLog (unchanged):
* doc/invoke.texi: Clarify AArch64 feature modifiers (no)fp, (no)simd
and (no)crypto.
OK.
Thanks,
James
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index
d8e982c3aa338819df3785696c493a66c1f5b674..0579bf2ecf993bb56987e0bb9686925537ab61e3
100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -12359,7 +12359,10 @@ Generate big-endian code. This is the default when
GCC is configured for an
@item -mgeneral-regs-only
@opindex mgeneral-regs-only
-Generate code which uses only the general registers.
+Generate code which uses only the general-purpose registers. This is
equivalent
+to feature modifier @option{nofp} of @option{-march} or @option{-mcpu},
except
+that @option{-mgeneral-regs-only} takes precedence over any conflicting
feature
+modifier regardless of sequence.
@item -mlittle-endian
@opindex mlittle-endian
@@ -12498,20 +12501,22 @@ over the appropriate part of this option.
@subsubsection @option{-march} and @option{-mcpu} Feature Modifiers
@cindex @option{-march} feature modifiers
@cindex @option{-mcpu} feature modifiers
-Feature modifiers used with @option{-march} and @option{-mcpu} can be one
-the following:
+Feature modifiers used with @option{-march} and @option{-mcpu} can be any of
+the following and their inverses @option{no@var{feature}}:
@table @samp
@item crc
Enable CRC extension.
@item crypto
-Enable Crypto extension. This implies Advanced SIMD is enabled.
+Enable Crypto extension. This also enables Advanced SIMD and floating-point
+instructions.
@item fp
-Enable floating-point instructions.
+Enable floating-point instructions. This is on by default for all possible
+values for options @option{-march} and @option{-mcpu}.
@item simd
-Enable Advanced SIMD instructions. This implies floating-point instructions
-are enabled. This is the default for all current possible values for options
-@option{-march} and @option{-mcpu=}.
+Enable Advanced SIMD instructions. This also enables floating-point
+instructions. This is on by default for all possible values for options
+@option{-march} and @option{-mcpu}.
@item lse
Enable Large System Extension instructions.
@item pan
@@ -12522,6 +12527,10 @@ Enable Limited Ordering Regions support.
Enable ARMv8.1 Advanced SIMD instructions.
@end table
+That is, @option{crypto} implies @option{simd} implies @option{fp}.
+Conversely, @option{nofp} (or equivalently, @option{-mgeneral-regs-only})
+implies @option{nosimd} implies @option{nocrypto}.
+
@node Adapteva Epiphany Options
@subsection Adapteva Epiphany Options
[PATCH 2/3][AArch64 nofp] Clarify docs for +nofp/-mgeneral-regs-only
James Greenhalgh wrote:
-Generate code which uses only the general registers.
+Generate code which uses only the general registers. Equivalent to feature
The ARMARM uses general-purpose registers to refer to these registers,
we should match that style.
s/Equivalent to feature/This is equivalent to the feature/
Done.
-Feature modifiers used with @option{-march} and @option{-mcpu} can be one
-the following:
+Feature modifiers used with @option{-march} and @option{-mcpu} can be any of
+the following, or their inverses @option{no@var{feature}}:
s/inverses/inverse/
The grammar is quite difficult here, so have gone for and their inverses as
the set of possibilities definitely includes 3 inverses.
+As stated above, @option{crypto} implies @option{simd} implies @option{fp}.
Drop the As stated above.
To my eye, beginning a sentence in lowercase looks very odd in pdf, and still a
bit odd in html. Have changed to That is...?
Tested with make pdf make html.
gcc/ChangeLog (unchanged):
* doc/invoke.texi: Clarify AArch64 feature modifiers (no)fp, (no)simd
and (no)crypto.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index d8e982c3aa338819df3785696c493a66c1f5b674..0579bf2ecf993bb56987e0bb9686925537ab61e3 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -12359,7 +12359,10 @@ Generate big-endian code. This is the default when GCC is configured for an
@item -mgeneral-regs-only
@opindex mgeneral-regs-only
-Generate code which uses only the general registers.
+Generate code which uses only the general-purpose registers. This is equivalent
+to feature modifier @option{nofp} of @option{-march} or @option{-mcpu}, except
+that @option{-mgeneral-regs-only} takes precedence over any conflicting feature
+modifier regardless of sequence.
@item -mlittle-endian
@opindex mlittle-endian
@@ -12498,20 +12501,22 @@ over the appropriate part of this option.
@subsubsection @option{-march} and @option{-mcpu} Feature Modifiers
@cindex @option{-march} feature modifiers
@cindex @option{-mcpu} feature modifiers
-Feature modifiers used with @option{-march} and @option{-mcpu} can be one
-the following:
+Feature modifiers used with @option{-march} and @option{-mcpu} can be any of
+the following and their inverses @option{no@var{feature}}:
@table @samp
@item crc
Enable CRC extension.
@item crypto
-Enable Crypto extension. This implies Advanced SIMD is enabled.
+Enable Crypto extension. This also enables Advanced SIMD and floating-point
+instructions.
@item fp
-Enable floating-point instructions.
+Enable floating-point instructions. This is on by default for all possible
+values for options @option{-march} and @option{-mcpu}.
@item simd
-Enable Advanced SIMD instructions. This implies floating-point instructions
-are enabled. This is the default for all current possible values for options
-@option{-march} and @option{-mcpu=}.
+Enable Advanced SIMD instructions. This also enables floating-point
+instructions. This is on by default for all possible values for options
+@option{-march} and @option{-mcpu}.
@item lse
Enable Large System Extension instructions.
@item pan
@@ -12522,6 +12527,10 @@ Enable Limited Ordering Regions support.
Enable ARMv8.1 Advanced SIMD instructions.
@end table
+That is, @option{crypto} implies @option{simd} implies @option{fp}.
+Conversely, @option{nofp} (or equivalently, @option{-mgeneral-regs-only})
+implies @option{nosimd} implies @option{nocrypto}.
+
@node Adapteva Epiphany Options
@subsection Adapteva Epiphany Options
