Re: [PATCH 2/3] [ARC] Add scaled load pattern

[Claudiu Zissulescu]

You are right, I should start with cleaning up the movsi pattern :) I
will come back to you with a proper patch when it is ready.

Thank you,
Claudiu

On Wed, Nov 20, 2019 at 2:00 AM Jeff Law  wrote:
>
> On 11/19/19 2:02 AM, Claudiu Zissulescu wrote:
> > ARC processors can use scaled addresses, i.e., the offset part of the
> > load address can be shifted by 2 (multiplied by 4). Add this pattern
> > and a test for it.
> >
> > gcc/
> > -xx-xx  Claudiu Zissulescu  
> >
> >   * config/arc/arc.md (load_scaledsi): New pattern.
> >
> > testcase/
> > -xx-xx  Claudiu Zissulescu  
> >
> >   * gcc.target/arc/scaled-ld.c: New test.
> This is worrisome.  I'm pretty sure this has to be folded into the
> existing move pattern to satisfy obscure reload requirements.
>
> Jeff
>

Re: [PATCH 2/3] [ARC] Add scaled load pattern

[Jeff Law]

On 11/19/19 2:02 AM, Claudiu Zissulescu wrote:
> ARC processors can use scaled addresses, i.e., the offset part of the
> load address can be shifted by 2 (multiplied by 4). Add this pattern
> and a test for it.
> 
> gcc/
> -xx-xx  Claudiu Zissulescu  
> 
>   * config/arc/arc.md (load_scaledsi): New pattern.
> 
> testcase/
> -xx-xx  Claudiu Zissulescu  
> 
>   * gcc.target/arc/scaled-ld.c: New test.
This is worrisome.  I'm pretty sure this has to be folded into the
existing move pattern to satisfy obscure reload requirements.

Jeff

[PATCH 2/3] [ARC] Add scaled load pattern

[Claudiu Zissulescu]

ARC processors can use scaled addresses, i.e., the offset part of the
load address can be shifted by 2 (multiplied by 4). Add this pattern
and a test for it.

gcc/
-xx-xx  Claudiu Zissulescu  

* config/arc/arc.md (load_scaledsi): New pattern.

testcase/
-xx-xx  Claudiu Zissulescu  

* gcc.target/arc/scaled-ld.c: New test.
---
 gcc/config/arc/arc.md| 12 
 gcc/testsuite/gcc.target/arc/scaled-ld.c | 13 +
 2 files changed, 25 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/arc/scaled-ld.c

diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index d2b7a45b6e6..ed16be65cab 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -867,6 +867,18 @@ archs4x, archs4xd"
   "st%U0 %1,%0\;st%U0.di %1,%0"
   [(set_attr "type" "store")])
 
+(define_insn "*load_scaledsi"
+  [(set (match_operand:SI 0 "register_operand" "=q,r,r")
+   (mem:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" 
"q,r,r")
+ (const_int 4))
+(match_operand:SI 2 "nonmemory_operand" "q,r,Cal"]
+  ""
+  "ld%?.as\\t%0,[%2,%1]"
+  [(set_attr "type" "load")
+   (set_attr "iscompact" "true,false,false")
+   (set_attr "length" "2,4,8")
+   (set_attr "cpu_facility" "cd,*,*")])
+
 ;; Combiner patterns for compare with zero
 (define_mode_iterator SQH [QI HI])
 (define_mode_attr SQH_postfix [(QI "b") (HI "%_")])
diff --git a/gcc/testsuite/gcc.target/arc/scaled-ld.c 
b/gcc/testsuite/gcc.target/arc/scaled-ld.c
new file mode 100644
index 000..bebae8fe505
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/scaled-ld.c
@@ -0,0 +1,13 @@
+/* Simple test for scaled load addressed.  */
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+const int table[2] = {1, 2};
+
+int
+foo (char i)
+{
+  return table[i];
+}
+
+/* { dg-final { scan-assembler "ld.as" } } */
-- 
2.23.0