Re: [PATCH 2/5] RISC-V: Add Types for Un-Typed zc Instructions

2023-09-07 Thread Edwin Lu 



On 9/6/2023 4:33 PM, Kito Cheng wrote:
csr is kind of confusing, I would suggest something like `pushpop` and 
`mvpair`.



Sounds good! I'll make the update.

Edwin

Re: [PATCH 2/5] RISC-V: Add Types for Un-Typed zc Instructions

2023-09-06 Thread Kito Cheng via Gcc-patches 
csr is kind of confusing, I would suggest something like `pushpop` and
`mvpair`.

Edwin Lu  於 2023年9月7日 週四 01:51 寫道：

> This patch adds types to the untyped zc instructions. Creates a new
> type "csr" for these instructions for now.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Add "csr" type
> * config/riscv/zc.md: Update types
>
> Signed-off-by: Edwin Lu 
> ---
>  gcc/config/riscv/riscv.md |   3 +-
>  gcc/config/riscv/zc.md| 102 +++---
>  2 files changed, 54 insertions(+), 51 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index d80b6938f84..6684ad89cff 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -312,6 +312,7 @@ (define_attr "ext_enabled" "no,yes"
>  ;; condmoveconditional moves
>  ;; cbocache block instructions
>  ;; crypto cryptography instructions
> +;; csrcode size reduction instructions
>  ;; Classification of RVV instructions which will be added to each RVV .md
> pattern and used by scheduler.
>  ;; rdvlenb vector byte length vlenb csrr read
>  ;; rdvlvector length vl csrr read
> @@ -421,7 +422,7 @@ (define_attr "type"
> mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
> fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip,
> rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
> -   atomic,condmove,cbo,crypto,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
> +   atomic,condmove,cbo,crypto,csr,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
> vlde,vste,vldm,vstm,vlds,vsts,
> vldux,vldox,vstux,vstox,vldff,vldr,vstr,
>
> vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,
> diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md
> index 77b28adde95..86f1afd66cb 100644
> --- a/gcc/config/riscv/zc.md
> +++ b/gcc/config/riscv/zc.md
> @@ -27,7 +27,7 @@ (define_insn "@gpr_multi_pop_up_to_ra_"
> (const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra}, %0"
> -)
> +[(set_attr "type" "csr")])
>
>  (define_insn "@gpr_multi_pop_up_to_s0_"
>[(set (reg:X SP_REGNUM)
> @@ -41,7 +41,7 @@ (define_insn "@gpr_multi_pop_up_to_s0_"
> (const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra, s0}, %0"
> -)
> +[(set_attr "type" "csr")])
>
>  (define_insn "@gpr_multi_pop_up_to_s1_"
>[(set (reg:X SP_REGNUM)
> @@ -58,7 +58,7 @@ (define_insn "@gpr_multi_pop_up_to_s1_"
> (const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra, s0-s1}, %0"
> -)
> +[(set_attr "type" "csr")])
>
>  (define_insn "@gpr_multi_pop_up_to_s2_"
>[(set (reg:X SP_REGNUM)
> @@ -78,7 +78,7 @@ (define_insn "@gpr_multi_pop_up_to_s2_"
> (const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra, s0-s2}, %0"
> -)
> +[(set_attr "type" "csr")])
>
>  (define_insn "@gpr_multi_pop_up_to_s3_"
>[(set (reg:X SP_REGNUM)
> @@ -101,7 +101,7 @@ (define_insn "@gpr_multi_pop_up_to_s3_"
> (const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra, s0-s3}, %0"
> -)
> +[(set_attr "type" "csr")])
>
>  (define_insn "@gpr_multi_pop_up_to_s4_"
>[(set (reg:X SP_REGNUM)
> @@ -127,7 +127,7 @@ (define_insn "@gpr_multi_pop_up_to_s4_"
> (const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra, s0-s4}, %0"
> -)
> +[(set_attr "type" "csr")])
>
>  (define_insn "@gpr_multi_pop_up_to_s5_"
>[(set (reg:X SP_REGNUM)
> @@ -156,7 +156,7 @@ (define_insn "@gpr_multi_pop_up_to_s5_"
> (const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra, s0-s5}, %0"
> -)
> +[(set_attr "type" "csr")])
>
>  (define_insn "@gpr_multi_pop_up_to_s6_"
>[(set (reg:X SP_REGNUM)
> @@ -188,7 +188,7 @@ (define_insn "@gpr_multi_pop_up_to_s6_"
> (const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra, s0-s6}, %0"
> -)
> +[(set_attr "type" "csr")])
>
>  (define_insn "@gpr_multi_pop_up_to_s7_"
>[(set (reg:X SP_REGNUM)
> @@ -223,7 +223,7 @@ (define_insn "@gpr_multi_pop_up_to_s7_"
>(const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra, s0-s7}, %0"
> -)
> +[(set_attr "type" "csr")])
>
>  (define_insn "@gpr_multi_pop_up_to_s8_"
>[(set (reg:X SP_REGNUM)
> @@ -261,7 +261,7 @@ (define_insn "@gpr_multi_pop_up_to_s8_"
> (const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra, s0-s8}, %0"
> -)
> +[(set_attr "type" "csr")])
>
>  (define_insn "@gpr_multi_pop_up_to_s9_"
>[(set (reg:X SP_REGNUM)
> @@ -302,7 +302,7 @@ (define_insn "@gpr_multi_pop_up_to_s9_"
> (const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra, s0-s9}, %0"
> -)
> +[(set_attr "type" "csr")])
>
>  (define_insn "@gpr_multi_pop_up_to_s11_"
>[(set (reg:X SP_REGNUM)
> @@ -349,7 +349,7 @@ (define_insn "@gpr_multi_pop_up_to_s11_"
> (const_int ]
>"TARGET_ZCMP"
>"cm.pop  {ra, s0-s11}, %0"
> -)
> +[(set_attr "type"

[PATCH 2/5] RISC-V: Add Types for Un-Typed zc Instructions

2023-09-06 Thread Edwin Lu 
This patch adds types to the untyped zc instructions. Creates a new
type "csr" for these instructions for now.

gcc/ChangeLog:

* config/riscv/riscv.md: Add "csr" type
* config/riscv/zc.md: Update types

Signed-off-by: Edwin Lu 
---
 gcc/config/riscv/riscv.md |   3 +-
 gcc/config/riscv/zc.md| 102 +++---
 2 files changed, 54 insertions(+), 51 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index d80b6938f84..6684ad89cff 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -312,6 +312,7 @@ (define_attr "ext_enabled" "no,yes"
 ;; condmoveconditional moves
 ;; cbocache block instructions
 ;; crypto cryptography instructions
+;; csrcode size reduction instructions
 ;; Classification of RVV instructions which will be added to each RVV .md 
pattern and used by scheduler.
 ;; rdvlenb vector byte length vlenb csrr read
 ;; rdvlvector length vl csrr read
@@ -421,7 +422,7 @@ (define_attr "type"
mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip,
rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
-   atomic,condmove,cbo,crypto,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
+   atomic,condmove,cbo,crypto,csr,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
vlde,vste,vldm,vstm,vlds,vsts,
vldux,vldox,vstux,vstox,vldff,vldr,vstr,

vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,
diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md
index 77b28adde95..86f1afd66cb 100644
--- a/gcc/config/riscv/zc.md
+++ b/gcc/config/riscv/zc.md
@@ -27,7 +27,7 @@ (define_insn "@gpr_multi_pop_up_to_ra_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_pop_up_to_s0_"
   [(set (reg:X SP_REGNUM)
@@ -41,7 +41,7 @@ (define_insn "@gpr_multi_pop_up_to_s0_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_pop_up_to_s1_"
   [(set (reg:X SP_REGNUM)
@@ -58,7 +58,7 @@ (define_insn "@gpr_multi_pop_up_to_s1_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s1}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_pop_up_to_s2_"
   [(set (reg:X SP_REGNUM)
@@ -78,7 +78,7 @@ (define_insn "@gpr_multi_pop_up_to_s2_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s2}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_pop_up_to_s3_"
   [(set (reg:X SP_REGNUM)
@@ -101,7 +101,7 @@ (define_insn "@gpr_multi_pop_up_to_s3_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s3}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_pop_up_to_s4_"
   [(set (reg:X SP_REGNUM)
@@ -127,7 +127,7 @@ (define_insn "@gpr_multi_pop_up_to_s4_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s4}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_pop_up_to_s5_"
   [(set (reg:X SP_REGNUM)
@@ -156,7 +156,7 @@ (define_insn "@gpr_multi_pop_up_to_s5_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s5}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_pop_up_to_s6_"
   [(set (reg:X SP_REGNUM)
@@ -188,7 +188,7 @@ (define_insn "@gpr_multi_pop_up_to_s6_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s6}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_pop_up_to_s7_"
   [(set (reg:X SP_REGNUM)
@@ -223,7 +223,7 @@ (define_insn "@gpr_multi_pop_up_to_s7_"
   (const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s7}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_pop_up_to_s8_"
   [(set (reg:X SP_REGNUM)
@@ -261,7 +261,7 @@ (define_insn "@gpr_multi_pop_up_to_s8_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s8}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_pop_up_to_s9_"
   [(set (reg:X SP_REGNUM)
@@ -302,7 +302,7 @@ (define_insn "@gpr_multi_pop_up_to_s9_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s9}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_pop_up_to_s11_"
   [(set (reg:X SP_REGNUM)
@@ -349,7 +349,7 @@ (define_insn "@gpr_multi_pop_up_to_s11_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s11}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_popret_up_to_ra_"
   [(set (reg:X SP_REGNUM)
@@ -362,7 +362,7 @@ (define_insn "@gpr_multi_popret_up_to_ra_"
(use (reg:SI RETURN_ADDR_REGNUM))]
   "TARGET_ZCMP"
   "cm.popret   {ra}, %0"
-)
+[(set_attr "type" "csr")])
 
 (define_insn "@gpr_multi_popret_up_to_s0_"
   [(set (reg:X SP_REGNUM)
@@ -378,7 +378,7 @@ (define_insn