RE: [PATCH 2/7] [ARC] Avoid use of hard registers before reg-alloc.

2017-06-01 Thread Claudiu Zissulescu 
> Looks good, thanks,

Committed, thank you,
Claudiu

Re: [PATCH 2/7] [ARC] Avoid use of hard registers before reg-alloc.

2017-05-31 Thread Andrew Burgess 
* Claudiu Zissulescu  [2017-05-19 12:30:57 
+0200]:

> gcc/
> 2017-04-10  Claudiu Zissulescu  
> 
>   * config/arc/arc.md (mulsi3): Avoid use of hard registers before
>   reg-alloc when having mul64 or mul32x16 instructions.
>   (mulsidi3): Likewise.
>   (umulsidi3): Likewise.
>   (mulsi32x16): New pattern.
>   (mulsi64): Likewise.
>   (mulsidi64): Likewise.
>   (umulsidi64): Likewise.
>   (MUL32x16_REG): Define.
>   (mul64_600): Use MUL32x16_REG.
>   (mac64_600): Likewise.
>   (umul64_600): Likewise.
>   (umac64_600): Likewise.


Looks good, thanks,

Andrew

> ---
>  gcc/config/arc/arc.md | 168 
> +++---
>  1 file changed, 119 insertions(+), 49 deletions(-)
> 
> diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
> index db5867c..c0ad86c 100644
> --- a/gcc/config/arc/arc.md
> +++ b/gcc/config/arc/arc.md
> @@ -176,6 +176,7 @@
> (ILINK2_REGNUM 30)
> (RETURN_ADDR_REGNUM 31)
> (MUL64_OUT_REG 58)
> +   (MUL32x16_REG 56)
> (ARCV2_ACC 58)
>  
> (LP_COUNT 60)
> @@ -1940,29 +1941,17 @@
>  }
>else if (TARGET_MUL64_SET)
>  {
> -  emit_insn (gen_mulsi_600 (operands[1], operands[2],
> - gen_mlo (), gen_mhi ()));
> -  emit_move_insn (operands[0], gen_mlo ());
> -  DONE;
> + rtx tmp = gen_reg_rtx (SImode);
> + emit_insn (gen_mulsi64 (tmp, operands[1], operands[2]));
> + emit_move_insn (operands[0], tmp);
> + DONE;
>  }
>else if (TARGET_MULMAC_32BY16_SET)
>  {
> -  if (immediate_operand (operands[2], SImode)
> -   && INTVAL (operands[2]) >= 0
> -   && INTVAL (operands[2]) <= 65535)
> - {
> -   emit_insn (gen_umul_600 (operands[1], operands[2],
> -  gen_acc2 (), gen_acc1 ()));
> -   emit_move_insn (operands[0], gen_acc2 ());
> -   DONE;
> - }
> -  operands[2] = force_reg (SImode, operands[2]);
> -  emit_insn (gen_umul_600 (operands[1], operands[2],
> -gen_acc2 (), gen_acc1 ()));
> -  emit_insn (gen_mac_600 (operands[1], operands[2],
> -gen_acc2 (), gen_acc1 ()));
> -  emit_move_insn (operands[0], gen_acc2 ());
> -  DONE;
> + rtx tmp = gen_reg_rtx (SImode);
> + emit_insn (gen_mulsi32x16 (tmp, operands[1], operands[2]));
> + emit_move_insn (operands[0], tmp);
> + DONE;
>  }
>else
>  {
> @@ -1974,6 +1963,35 @@
>  }
>  })
>  
> +(define_insn_and_split "mulsi32x16"
> + [(set (match_operand:SI 0 "register_operand""=w")
> + (mult:SI (match_operand:SI 1 "register_operand"  "%c")
> +  (match_operand:SI 2 "nonmemory_operand" "ci")))
> +  (clobber (reg:DI MUL32x16_REG))]
> + "TARGET_MULMAC_32BY16_SET"
> + "#"
> + "TARGET_MULMAC_32BY16_SET && reload_completed"
> + [(const_int 0)]
> + {
> +  if (immediate_operand (operands[2], SImode)
> +&& INTVAL (operands[2]) >= 0
> +&& INTVAL (operands[2]) <= 65535)
> + {
> +  emit_insn (gen_umul_600 (operands[1], operands[2],
> +gen_acc2 (), gen_acc1 ()));
> +  emit_move_insn (operands[0], gen_acc2 ());
> +  DONE;
> + }
> +   emit_insn (gen_umul_600 (operands[1], operands[2],
> +gen_acc2 (), gen_acc1 ()));
> +   emit_insn (gen_mac_600 (operands[1], operands[2],
> +gen_acc2 (), gen_acc1 ()));
> +   emit_move_insn (operands[0], gen_acc2 ());
> +   DONE;
> +  }
> + [(set_attr "type" "multi")
> +  (set_attr "length" "8")])
> +
>  ; mululw conditional execution without a LIMM clobbers an input register;
>  ; we'd need a different pattern to describe this.
>  ; To make the conditional execution valid for the LIMM alternative, we
> @@ -2011,6 +2029,24 @@
> (set_attr "predicable" "no, no, yes")
> (set_attr "cond" "nocond, canuse_limm, canuse")])
>  
> +(define_insn_and_split "mulsi64"
> + [(set (match_operand:SI 0 "register_operand""=w")
> + (mult:SI (match_operand:SI 1 "register_operand"  "%c")
> +  (match_operand:SI 2 "nonmemory_operand" "ci")))
> +  (clobber (reg:DI MUL64_OUT_REG))]
> + "TARGET_MUL64_SET"
> + "#"
> + "TARGET_MUL64_SET && reload_completed"
> +  [(const_int 0)]
> +{
> +  emit_insn (gen_mulsi_600 (operands[1], operands[2],
> + gen_mlo (), gen_mhi ()));
> +  emit_move_insn (operands[0], gen_mlo ());
> +  DONE;
> +}
> +  [(set_attr "type" "multi")
> +   (set_attr "length" "8")])
> +
>  (define_insn "mulsi_600"
>[(set (match_operand:SI 2 "mlo_operand" "")
>   (mult:SI (match_operand:SI 0 "register_operand"  "%Rcq#q,c,c,c")
> @@ -2155,8 +2191,7 @@
>   (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
>(sign_extend:DI (match_operand:SI 2 "nonmemory_operand" ""]
>"TARGET_ANY_MPY"
> -"
> -{
> +  {
>if

[PATCH 2/7] [ARC] Avoid use of hard registers before reg-alloc.

2017-05-19 Thread Claudiu Zissulescu 
gcc/
2017-04-10  Claudiu Zissulescu  

* config/arc/arc.md (mulsi3): Avoid use of hard registers before
reg-alloc when having mul64 or mul32x16 instructions.
(mulsidi3): Likewise.
(umulsidi3): Likewise.
(mulsi32x16): New pattern.
(mulsi64): Likewise.
(mulsidi64): Likewise.
(umulsidi64): Likewise.
(MUL32x16_REG): Define.
(mul64_600): Use MUL32x16_REG.
(mac64_600): Likewise.
(umul64_600): Likewise.
(umac64_600): Likewise.
---
 gcc/config/arc/arc.md | 168 +++---
 1 file changed, 119 insertions(+), 49 deletions(-)

diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index db5867c..c0ad86c 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -176,6 +176,7 @@
(ILINK2_REGNUM 30)
(RETURN_ADDR_REGNUM 31)
(MUL64_OUT_REG 58)
+   (MUL32x16_REG 56)
(ARCV2_ACC 58)
 
(LP_COUNT 60)
@@ -1940,29 +1941,17 @@
 }
   else if (TARGET_MUL64_SET)
 {
-  emit_insn (gen_mulsi_600 (operands[1], operands[2],
-   gen_mlo (), gen_mhi ()));
-  emit_move_insn (operands[0], gen_mlo ());
-  DONE;
+ rtx tmp = gen_reg_rtx (SImode);
+ emit_insn (gen_mulsi64 (tmp, operands[1], operands[2]));
+ emit_move_insn (operands[0], tmp);
+ DONE;
 }
   else if (TARGET_MULMAC_32BY16_SET)
 {
-  if (immediate_operand (operands[2], SImode)
- && INTVAL (operands[2]) >= 0
- && INTVAL (operands[2]) <= 65535)
-   {
- emit_insn (gen_umul_600 (operands[1], operands[2],
-gen_acc2 (), gen_acc1 ()));
- emit_move_insn (operands[0], gen_acc2 ());
- DONE;
-   }
-  operands[2] = force_reg (SImode, operands[2]);
-  emit_insn (gen_umul_600 (operands[1], operands[2],
-  gen_acc2 (), gen_acc1 ()));
-  emit_insn (gen_mac_600 (operands[1], operands[2],
-  gen_acc2 (), gen_acc1 ()));
-  emit_move_insn (operands[0], gen_acc2 ());
-  DONE;
+ rtx tmp = gen_reg_rtx (SImode);
+ emit_insn (gen_mulsi32x16 (tmp, operands[1], operands[2]));
+ emit_move_insn (operands[0], tmp);
+ DONE;
 }
   else
 {
@@ -1974,6 +1963,35 @@
 }
 })
 
+(define_insn_and_split "mulsi32x16"
+ [(set (match_operand:SI 0 "register_operand""=w")
+   (mult:SI (match_operand:SI 1 "register_operand"  "%c")
+(match_operand:SI 2 "nonmemory_operand" "ci")))
+  (clobber (reg:DI MUL32x16_REG))]
+ "TARGET_MULMAC_32BY16_SET"
+ "#"
+ "TARGET_MULMAC_32BY16_SET && reload_completed"
+ [(const_int 0)]
+ {
+  if (immediate_operand (operands[2], SImode)
+&& INTVAL (operands[2]) >= 0
+&& INTVAL (operands[2]) <= 65535)
+ {
+  emit_insn (gen_umul_600 (operands[1], operands[2],
+  gen_acc2 (), gen_acc1 ()));
+  emit_move_insn (operands[0], gen_acc2 ());
+  DONE;
+ }
+   emit_insn (gen_umul_600 (operands[1], operands[2],
+  gen_acc2 (), gen_acc1 ()));
+   emit_insn (gen_mac_600 (operands[1], operands[2],
+  gen_acc2 (), gen_acc1 ()));
+   emit_move_insn (operands[0], gen_acc2 ());
+   DONE;
+  }
+ [(set_attr "type" "multi")
+  (set_attr "length" "8")])
+
 ; mululw conditional execution without a LIMM clobbers an input register;
 ; we'd need a different pattern to describe this.
 ; To make the conditional execution valid for the LIMM alternative, we
@@ -2011,6 +2029,24 @@
(set_attr "predicable" "no, no, yes")
(set_attr "cond" "nocond, canuse_limm, canuse")])
 
+(define_insn_and_split "mulsi64"
+ [(set (match_operand:SI 0 "register_operand""=w")
+   (mult:SI (match_operand:SI 1 "register_operand"  "%c")
+(match_operand:SI 2 "nonmemory_operand" "ci")))
+  (clobber (reg:DI MUL64_OUT_REG))]
+ "TARGET_MUL64_SET"
+ "#"
+ "TARGET_MUL64_SET && reload_completed"
+  [(const_int 0)]
+{
+  emit_insn (gen_mulsi_600 (operands[1], operands[2],
+   gen_mlo (), gen_mhi ()));
+  emit_move_insn (operands[0], gen_mlo ());
+  DONE;
+}
+  [(set_attr "type" "multi")
+   (set_attr "length" "8")])
+
 (define_insn "mulsi_600"
   [(set (match_operand:SI 2 "mlo_operand" "")
(mult:SI (match_operand:SI 0 "register_operand"  "%Rcq#q,c,c,c")
@@ -2155,8 +2191,7 @@
(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
 (sign_extend:DI (match_operand:SI 2 "nonmemory_operand" ""]
   "TARGET_ANY_MPY"
-"
-{
+  {
   if (TARGET_PLUS_MACD)
 {
  if (CONST_INT_P (operands[2]))
@@ -2189,18 +2224,37 @@
 }
   else if (TARGET_MULMAC_32BY16_SET)
 {
-  rtx result_hi = gen_highpart(SImode, operands[0]);
-  rtx result_low = gen_lowpart(SImode, operands[0]);
-
-  emit_insn (gen_mul64_600 (operands[1], operands[2]));
-