subject:"\[PATCH 3\/4\]\[x86\] Add clwb,pcommit,avx512avbmi,avx512ifma."

Re: [PATCH 3/4][x86] Add clwb,pcommit,avx512avbmi,avx512ifma.

2014-11-21 Thread Ilya Tocar

On 20 Nov 09:43, Uros Bizjak wrote:
 On Wed, Nov 19, 2014 at 6:32 PM, Ilya Tocar tocarip.in...@gmail.com wrote:
  Hi,
 
  New revision of Intel ISA reference [1] has new instructions:
  Clwb, pcommit and new flavors of AVX512. Patch bellow adds them.
  I understand that stage 1 is closed, however those changes shouldn't
  affect anything outside if i386 backend. And are extremely unlikely to
  break existing functionality, and I personally think it's desirable for
  newest GCC to support newest spec.
  Bootstrapped/regtestsed on x86_64-unknown-linux-gnu.
  Ok for trunk?
 
 Please split the patch into patch series, like it was done previously
 for AVX512F patches.
 
 Uros.

Done. This part adds clwb.
Bootstrapped/passes make-check.
Ok for trunk?

gcc/

* common/config/i386/i386-common.c (OPTION_MASK_ISA_CLWB_UNSET,
OPTION_MASK_ISA_CLWB_SET): New.
(ix86_handle_option): Handle OPT_mclwb.
* config.gcc: Add clwbintrin.h.
* config/i386/clwbintrin.h: New file.
* config/i386/cpuid.h (bit_CLWB): Define.
* config/i386/driver-i386.c (host_detect_local_cpu): Detect clwb. 
* config/i386/i386-c.c (ix86_target_macros_internal): Define
__CLWB__.
* config/i386/i386.c (ix86_target_string): Add -mclwb.
(PTA_CLWB): Define.
(ix86_option_override_internal): Handle new option.
(ix86_valid_target_attribute_inner_p): Add clwb.
(ix86_builtins): Add IX86_BUILTIN_CLWB.
(ix86_init_mmx_sse_builtins): Add __builtin_ia32_clwb.
(ix86_expand_builtin): Handle IX86_BUILTIN_CLWB.
* config/i386/i386.h (TARGET_CLWB, TARGET_CLWB_P): Define.
* config/i386/i386.md (unspecv): Add UNSPECV_CLWB.
(clwb): New instruction.
* config/i386/i386.opt: Add mclwb.
* config/i386/x86intrin.h: Include clwbintrin.h.

gcc/testsuite/

* g++.dg/other/i386-2.C: Add -mclwb.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/clwb-1.c: New test.
* gcc.target/i386/sse-12.c: Add new options.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.

---
 gcc/common/config/i386/i386-common.c   | 15 +++
 gcc/config.gcc |  4 +--
 gcc/config/i386/clwbintrin.h   | 49 ++
 gcc/config/i386/cpuid.h|  1 +
 gcc/config/i386/driver-i386.c  |  6 +++--
 gcc/config/i386/i386-c.c   |  2 ++
 gcc/config/i386/i386.c | 23 
 gcc/config/i386/i386.h |  2 ++
 gcc/config/i386/i386.md| 12 +
 gcc/config/i386/i386.opt   |  4 +++
 gcc/config/i386/x86intrin.h|  2 ++
 gcc/testsuite/g++.dg/other/i386-2.C|  2 +-
 gcc/testsuite/g++.dg/other/i386-3.C|  2 +-
 gcc/testsuite/gcc.target/i386/clwb-1.c | 11 
 gcc/testsuite/gcc.target/i386/sse-12.c |  2 +-
 gcc/testsuite/gcc.target/i386/sse-13.c |  2 +-
 gcc/testsuite/gcc.target/i386/sse-14.c |  2 +-
 gcc/testsuite/gcc.target/i386/sse-22.c |  2 +-
 gcc/testsuite/gcc.target/i386/sse-23.c |  2 +-
 19 files changed, 134 insertions(+), 11 deletions(-)
 create mode 100644 gcc/config/i386/clwbintrin.h
 create mode 100644 gcc/testsuite/gcc.target/i386/clwb-1.c

diff --git a/gcc/common/config/i386/i386-common.c 
b/gcc/common/config/i386/i386-common.c
index 1c4f15e..bad0988 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -85,6 +85,7 @@ along with GCC; see the file COPYING3.  If not see
   (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE)
 #define OPTION_MASK_ISA_XSAVEC_SET \
   (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE)
+#define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
 
 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
as -msse4.2.  */
@@ -181,6 +182,7 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
 #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
 #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
+#define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
 
 /* SSE4 includes both SSE4.1 and SSE4.2.  -mno-sse4 should the same
as -mno-sse4.1. */
@@ -901,6 +903,19 @@ ix86_handle_option (struct gcc_options *opts,
}
   return true;
 
+case OPT_mclwb:
+  if (value)
+   {
+ opts-x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET;
+ opts-x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET;
+   }
+  else
+   {
+ opts-x_ix86_isa_flags = ~OPTION_MASK_ISA_CLWB_UNSET;
+ opts-x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET;
+   }
+  return true;
+
   /* Comes from final.c -- no real reason to change it.  */
 #define MAX_CODE_ALIGN 16
 
diff --git a/gcc/config.gcc b/gcc/config.gcc
index da2a723..766f13b 100644

Re: [PATCH 3/4][x86] Add clwb,pcommit,avx512avbmi,avx512ifma.

2014-11-21 Thread Uros Bizjak

On Fri, Nov 21, 2014 at 12:45 PM, Ilya Tocar tocarip.in...@gmail.com wrote:
 On 20 Nov 09:43, Uros Bizjak wrote:
 On Wed, Nov 19, 2014 at 6:32 PM, Ilya Tocar tocarip.in...@gmail.com wrote:
  Hi,
 
  New revision of Intel ISA reference [1] has new instructions:
  Clwb, pcommit and new flavors of AVX512. Patch bellow adds them.
  I understand that stage 1 is closed, however those changes shouldn't
  affect anything outside if i386 backend. And are extremely unlikely to
  break existing functionality, and I personally think it's desirable for
  newest GCC to support newest spec.
  Bootstrapped/regtestsed on x86_64-unknown-linux-gnu.
  Ok for trunk?

 Please split the patch into patch series, like it was done previously
 for AVX512F patches.

 Uros.

 Done. This part adds clwb.
 Bootstrapped/passes make-check.
 Ok for trunk?

 gcc/

 * common/config/i386/i386-common.c (OPTION_MASK_ISA_CLWB_UNSET,
 OPTION_MASK_ISA_CLWB_SET): New.
 (ix86_handle_option): Handle OPT_mclwb.
 * config.gcc: Add clwbintrin.h.
 * config/i386/clwbintrin.h: New file.
 * config/i386/cpuid.h (bit_CLWB): Define.
 * config/i386/driver-i386.c (host_detect_local_cpu): Detect clwb.
 * config/i386/i386-c.c (ix86_target_macros_internal): Define
 __CLWB__.
 * config/i386/i386.c (ix86_target_string): Add -mclwb.
 (PTA_CLWB): Define.
 (ix86_option_override_internal): Handle new option.
 (ix86_valid_target_attribute_inner_p): Add clwb.
 (ix86_builtins): Add IX86_BUILTIN_CLWB.
 (ix86_init_mmx_sse_builtins): Add __builtin_ia32_clwb.
 (ix86_expand_builtin): Handle IX86_BUILTIN_CLWB.
 * config/i386/i386.h (TARGET_CLWB, TARGET_CLWB_P): Define.
 * config/i386/i386.md (unspecv): Add UNSPECV_CLWB.
 (clwb): New instruction.
 * config/i386/i386.opt: Add mclwb.
 * config/i386/x86intrin.h: Include clwbintrin.h.

 gcc/testsuite/

 * g++.dg/other/i386-2.C: Add -mclwb.
 * g++.dg/other/i386-3.C: Ditto.
 * gcc.target/i386/clwb-1.c: New test.
 * gcc.target/i386/sse-12.c: Add new options.
 * gcc.target/i386/sse-13.c: Ditto.
 * gcc.target/i386/sse-14.c: Ditto.
 * gcc.target/i386/sse-22.c: Ditto.
 * gcc.target/i386/sse-23.c: Ditto.

OK.

Thanks,
Uros.

 ---
  gcc/common/config/i386/i386-common.c   | 15 +++
  gcc/config.gcc |  4 +--
  gcc/config/i386/clwbintrin.h   | 49 
 ++
  gcc/config/i386/cpuid.h|  1 +
  gcc/config/i386/driver-i386.c  |  6 +++--
  gcc/config/i386/i386-c.c   |  2 ++
  gcc/config/i386/i386.c | 23 
  gcc/config/i386/i386.h |  2 ++
  gcc/config/i386/i386.md| 12 +
  gcc/config/i386/i386.opt   |  4 +++
  gcc/config/i386/x86intrin.h|  2 ++
  gcc/testsuite/g++.dg/other/i386-2.C|  2 +-
  gcc/testsuite/g++.dg/other/i386-3.C|  2 +-
  gcc/testsuite/gcc.target/i386/clwb-1.c | 11 
  gcc/testsuite/gcc.target/i386/sse-12.c |  2 +-
  gcc/testsuite/gcc.target/i386/sse-13.c |  2 +-
  gcc/testsuite/gcc.target/i386/sse-14.c |  2 +-
  gcc/testsuite/gcc.target/i386/sse-22.c |  2 +-
  gcc/testsuite/gcc.target/i386/sse-23.c |  2 +-
  19 files changed, 134 insertions(+), 11 deletions(-)
  create mode 100644 gcc/config/i386/clwbintrin.h
  create mode 100644 gcc/testsuite/gcc.target/i386/clwb-1.c

 diff --git a/gcc/common/config/i386/i386-common.c 
 b/gcc/common/config/i386/i386-common.c
 index 1c4f15e..bad0988 100644
 --- a/gcc/common/config/i386/i386-common.c
 +++ b/gcc/common/config/i386/i386-common.c
 @@ -85,6 +85,7 @@ along with GCC; see the file COPYING3.  If not see
(OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE)
  #define OPTION_MASK_ISA_XSAVEC_SET \
(OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE)
 +#define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB

  /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
 as -msse4.2.  */
 @@ -181,6 +182,7 @@ along with GCC; see the file COPYING3.  If not see
  #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
  #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
  #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
 +#define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB

  /* SSE4 includes both SSE4.1 and SSE4.2.  -mno-sse4 should the same
 as -mno-sse4.1. */
 @@ -901,6 +903,19 @@ ix86_handle_option (struct gcc_options *opts,
 }
return true;

 +case OPT_mclwb:
 +  if (value)
 +   {
 + opts-x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET;
 + opts-x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET;
 +   }
 +  else
 +   {
 + opts-x_ix86_isa_flags = ~OPTION_MASK_ISA_CLWB_UNSET;
 + opts-x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET;
 +   }
 +

Re: [PATCH 3/4][x86] Add clwb,pcommit,avx512avbmi,avx512ifma.

Re: [PATCH 3/4][x86] Add clwb,pcommit,avx512avbmi,avx512ifma.

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