V2 changes:
1. remove xfail
2. testcase files naming harmonized with existing
---
Hi,
This patch add conditional unary neg/abs/not autovec patterns to RISC-V backend.
For this C code:
void
test_3 (float *__restrict a, float *__restrict b, int *__restrict pred, int n)
{
for (int i = 0; i < n; i += 1)
{
a[i] = pred[i] ? __builtin_fabsf (b[i]) : a[i];
}
}
Before this patch:
...
vsetvli a7,zero,e32,m1,ta,ma
vfabs.v v2,v2
vmerge.vvm v1,v1,v2,v0
...
After this patch:
...
vsetvli a7,zero,e32,m1,ta,mu
vfabs.v v1,v2,v0.t
...
For int neg/not and FP neg patterns, Defining the corresponding cond_xxx paterns
is enough.
For the FP abs pattern, We need to change the definition of `abs2` and
`@vcond_mask_` pattern from define_expand to define_insn_and_split
in order to fuse them into a new pattern `*cond_abs` at the combine pass.
A fusion process similar to the one below:
(insn 30 29 31 4 (set (reg:RVVM1SF 152 [ vect_iftmp.15 ])
(abs:RVVM1SF (reg:RVVM1SF 137 [ vect__6.14 ]))) "float.c":15:56 discrim
1 12799 {absrvvm1sf2}
(expr_list:REG_DEAD (reg:RVVM1SF 137 [ vect__6.14 ])
(nil)))
(insn 31 30 32 4 (set (reg:RVVM1SF 140 [ vect_iftmp.19 ])
(if_then_else:RVVM1SF (reg:RVVMF32BI 136 [ mask__27.11 ])
(reg:RVVM1SF 152 [ vect_iftmp.15 ])
(reg:RVVM1SF 139 [ vect_iftmp.18 ]))) 12707
{vcond_mask_rvvm1sfrvvmf32bi}
(expr_list:REG_DEAD (reg:RVVM1SF 152 [ vect_iftmp.15 ])
(expr_list:REG_DEAD (reg:RVVM1SF 139 [ vect_iftmp.18 ])
(expr_list:REG_DEAD (reg:RVVMF32BI 136 [ mask__27.11 ])
(nil)
==>
(insn 31 30 32 4 (set (reg:RVVM1SF 140 [ vect_iftmp.19 ])
(if_then_else:RVVM1SF (reg:RVVMF32BI 136 [ mask__27.11 ])
(abs:RVVM1SF (reg:RVVM1SF 137 [ vect__6.14 ]))
(reg:RVVM1SF 139 [ vect_iftmp.18 ]))) 13444 {*cond_absrvvm1sf}
(expr_list:REG_DEAD (reg:RVVM1SF 137 [ vect__6.14 ])
(expr_list:REG_DEAD (reg:RVVMF32BI 136 [ mask__27.11 ])
(expr_list:REG_DEAD (reg:RVVM1SF 139 [ vect_iftmp.18 ])
(nil)
Best,
Lehua
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*cond_abs): New combine pattern.
(*copysign_neg): Ditto.
* config/riscv/autovec.md (@vcond_mask_): Adjust.
(2): Ditto.
(cond_): New.
(cond_len_): Ditto.
* config/riscv/riscv-protos.h (enum insn_type): New.
(expand_cond_len_unop): New helper func.
* config/riscv/riscv-v.cc (shuffle_merge_patterns): Adjust.
(expand_cond_len_unop): New helper func.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-1.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-2.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-3.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-4.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-5.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-6.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-7.c: New test.
* gcc.target/riscv/rvv/autovec/cond/cond_unary_run-8.c: New test.
---
gcc/config/riscv/autovec-opt.md | 39
gcc/config/riscv/autovec.md | 97 +--
gcc/config/riscv/riscv-protos.h | 7 +-
gcc/config/riscv/riscv-v.cc | 56 ++-
.../riscv/rvv/autovec/cond/cond_unary-1.c | 43
.../riscv/rvv/autovec/cond/cond_unary-2.c | 46 +
.../riscv/rvv/autovec/cond/cond_unary-3.c | 43
.../riscv/rvv/autovec/cond/cond_unary-4.c | 43
.../riscv/rvv/autovec/cond/cond_unary-5.c | 36 +++
.../riscv/rvv/autovec/cond/cond_unary-6.c | 39
.../riscv/rvv/autovec/cond/cond_unary-7.c | 36 +++
.../riscv/rvv/autovec/cond/cond_unary-8.c | 36 +++
.../riscv/rvv/autovec/cond/cond_unary_run-1.c | 27 ++
.../riscv/rvv/autovec/cond/cond_unary_run-2.c | 28 ++
.../riscv/rvv/autovec/cond/cond_unary_run-3.c | 27 ++
.../riscv/rvv/autovec/cond/cond_unary_run-4.c | 27 ++
.../riscv/rvv/autovec/cond/cond_unary_run-5.c | 26 +
.../riscv/rvv/autovec/cond/cond_unary_run-6.c | 27 ++
.../riscv/rvv/autovec/cond/cond_unary_run-7.c | 26 +
.../riscv/rvv
