V3 changes: Address the comments from Robin.
Hi,
This patch refactors the codes of expand_cond_len_{unop,binop,ternop}.
Introduces a new unified function expand_cond_len_op to do the main thing.
The expand_cond_len_{unop,binop,ternop} functions only care about how
to pass the operands to the intrinsic patterns.
Best,
Lehua
gcc/ChangeLog:
* config/riscv/autovec.md: Adjust
* config/riscv/riscv-protos.h (RVV_VUNDEF): Clean.
(get_vlmax_rtx): Exported.
* config/riscv/riscv-v.cc (emit_nonvlmax_fp_ternary_tu_insn): Deleted.
(emit_vlmax_masked_gather_mu_insn): Adjust.
(get_vlmax_rtx): New func.
(expand_load_store): Adjust.
(expand_cond_len_unop): Call expand_cond_len_op.
(expand_cond_len_op): New subroutine.
(expand_cond_len_binop): Call expand_cond_len_op.
(expand_cond_len_ternop): Call expand_cond_len_op.
(expand_lanes_load_store): Adjust.
---
gcc/config/riscv/autovec.md | 6 +-
gcc/config/riscv/riscv-protos.h | 16 ++--
gcc/config/riscv/riscv-v.cc | 162 ++--
3 files changed, 58 insertions(+), 126 deletions(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 20ab0693b98..7a6247d9d6b 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -971,9 +971,9 @@
rtx mask = gen_reg_rtx (mask_mode);
riscv_vector::expand_vec_cmp (mask, LT, operands[1], zero);
- rtx ops[] = {operands[0], mask, operands[1], operands[1]};
- riscv_vector::emit_vlmax_masked_mu_insn (code_for_pred (NEG, mode),
- riscv_vector::RVV_UNOP_MU, ops);
+ rtx ops[] = {operands[0], mask, operands[1], operands[1],
+ riscv_vector::get_vlmax_rtx (mode)};
+ riscv_vector::expand_cond_len_unop (NEG, ops);
DONE;
})
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 0e0470280f8..4137bb14b80 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -181,25 +181,20 @@ namespace riscv_vector {
#define RVV_VUNDEF(MODE)
\
gen_rtx_UNSPEC (MODE, gen_rtvec (1, gen_rtx_REG (SImode, X0_REGNUM)),
\
UNSPEC_VUNDEF)
+
+/* The value means the number of operands for insn_expander. */
enum insn_type
{
RVV_MISC_OP = 1,
RVV_UNOP = 2,
- RVV_UNOP_M = RVV_UNOP + 2,
- RVV_UNOP_MU = RVV_UNOP + 2,
- RVV_UNOP_TU = RVV_UNOP + 2,
- RVV_UNOP_TUMU = RVV_UNOP + 2,
+ RVV_UNOP_MASK = RVV_UNOP + 2,
RVV_BINOP = 3,
- RVV_BINOP_MU = RVV_BINOP + 2,
- RVV_BINOP_TU = RVV_BINOP + 2,
- RVV_BINOP_TUMU = RVV_BINOP + 2,
+ RVV_BINOP_MASK = RVV_BINOP + 2,
RVV_MERGE_OP = 4,
RVV_CMP_OP = 4,
RVV_CMP_MU_OP = RVV_CMP_OP + 2, /* +2 means mask and maskoff operand. */
RVV_TERNOP = 5,
- RVV_TERNOP_MU = RVV_TERNOP + 1,
- RVV_TERNOP_TU = RVV_TERNOP + 1,
- RVV_TERNOP_TUMU = RVV_TERNOP + 1,
+ RVV_TERNOP_MASK = RVV_TERNOP + 1,
RVV_WIDEN_TERNOP = 4,
RVV_SCALAR_MOV_OP = 4, /* +1 for VUNDEF according to vector.md. */
RVV_SLIDE_OP = 4, /* Dest, VUNDEF, source and offset. */
@@ -260,6 +255,7 @@ void emit_vlmax_masked_mu_insn (unsigned, int, rtx *);
void emit_scalar_move_insn (unsigned, rtx *, rtx = 0);
void emit_nonvlmax_integer_move_insn (unsigned, rtx *, rtx);
enum vlmul_type get_vlmul (machine_mode);
+rtx get_vlmax_rtx (machine_mode);
unsigned int get_ratio (machine_mode);
unsigned int get_nf (machine_mode);
machine_mode get_subpart_mode (machine_mode);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index b783fb8ab00..bf247788659 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -761,28 +761,6 @@ emit_vlmax_fp_ternary_insn (unsigned icode, int op_num,
rtx *ops, rtx vl)
e.emit_insn ((enum insn_code) icode, ops);
}
-/* This function emits a {NONVLMAX, TAIL_UNDISTURBED, MASK_ANY} vsetvli
followed
- * by the ternary operation which always has a real merge operand. */
-static void
-emit_nonvlmax_fp_ternary_tu_insn (unsigned icode, int op_num, rtx *ops, rtx vl)
-{
- machine_mode dest_mode = GET_MODE (ops[0]);
- machine_mode mask_mode = get_mask_mode (dest_mode);
- insn_expander e (/*OP_NUM*/ op_num,
- /*HAS_DEST_P*/ true,
- /*FULLY_UNMASKED_P*/ false,
- /*USE_REAL_MERGE_P*/ true,
- /*HAS_AVL_P*/ true,
- /*VLMAX_P*/ false,
- /*DEST_MODE*/ dest_mode,
- /*MASK_MODE*/ mask_mode);
- e.set_policy (TAIL_UNDISTURBED);
- e.set_policy (MASK_ANY);
- e.set_rounding_mode (FRM_DYN);
- e.set_vl (vl);
- e.emit_insn ((enum insn_code) icode, ops);
-}
-
/* This function emits a {NONVLMAX, TAIL_ANY, MASK_ANY} vsetvli followed by the
*
