Re: [PATCH v1] RISC-V: Allow RVV intrinsic when function target("arch=+v")

2024-03-29 Thread Andreas Schwab 
../../gcc/config/riscv/riscv-vector-builtins.cc: In function 'rtx_def* 
riscv_vector::expand_builtin(unsigned int, tree, rtx)':
../../gcc/config/riscv/riscv-vector-builtins.cc:4592:16: error: misspelled term 
'builtin function' in format; use 'built-in function' instead 
[-Werror=format-diag]
 4592 |   "builtin function %qE requires the V ISA extension", exp);
  |^~~~
cc1plus: all warnings being treated as errors
make[3]: *** [../../gcc/config/riscv/t-riscv:28: riscv-vector-builtins.o] Error 
1

-- 
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510  2552 DF73 E780 A9DA AEC1
"And now for something completely different."

RE: [PATCH v1] RISC-V: Allow RVV intrinsic when function target("arch=+v")

2024-03-25 Thread Li, Pan2 
Committed, thanks kito.

Pan

-Original Message-
From: Kito Cheng  
Sent: Monday, March 25, 2024 8:04 PM
To: Li, Pan2 
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang 

Subject: Re: [PATCH v1] RISC-V: Allow RVV intrinsic when function 
target("arch=+v")

LGTM, thanks :)

On Mon, Mar 25, 2024 at 3:42 PM  wrote:
>
> From: Pan Li 
>
> This patch would like to allow the RVV intrinsic when function is
> attributed as target("arch=+v") and build with rv64gc.  For example:
>
> vint32m1_t
> __attribute__((target("arch=+v")))
> test_1 (vint32m1_t a, vint32m1_t b, size_t vl)
> {
>   return __riscv_vadd_vv_i32m1 (a, b, vl);
> }
>
> build with -march=rv64gc -mabi=lp64d -O3, we will have asm like below:
> test_1:
>   .option push
>   .option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_\
> zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
>   vsetvli zero,a0,e32,m1,ta,ma
>   vadd.vv v8,v8,v9
>   ret
>
> The riscv_vector.h must be included when leverage intrinisc type(s) and
> API(s).  And the scope of this attribute should not excced the function
> body.  Meanwhile, to make rvv types and API(s) available for this attribute,
> include riscv_vector.h will not report error for now if v is not present
> in march.
>
> Below test are passed for this patch:
> * The riscv fully regression test.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-c.cc (riscv_pragma_intrinsic): Remove error
> when V is disabled and init the RVV types and intrinic APIs.
> * config/riscv/riscv-vector-builtins.cc (expand_builtin): Report
> error if V ext is disabled.
> * config/riscv/riscv.cc (riscv_return_value_is_vector_type_p):
> Ditto.
> (riscv_arguments_is_vector_type_p): Ditto.
> (riscv_vector_cc_function_p): Ditto.
> * config/riscv/riscv_vector.h: Remove error if V is disable.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pragma-1.c: Remove.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-1.c: 
> New test.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-2.c: 
> New test.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c: 
> New test.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-4.c: 
> New test.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-5.c: 
> New test.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-6.c: 
> New test.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c: 
> New test.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c: 
> New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/riscv-c.cc   | 18 +++
>  gcc/config/riscv/riscv-vector-builtins.cc |  5 
>  gcc/config/riscv/riscv.cc | 30 ---
>  gcc/config/riscv/riscv_vector.h   |  4 ---
>  .../gcc.target/riscv/rvv/base/pragma-1.c  |  4 ---
>  .../target_attribute_v_with_intrinsic-1.c |  5 
>  .../target_attribute_v_with_intrinsic-2.c | 18 +++
>  .../target_attribute_v_with_intrinsic-3.c | 13 
>  .../target_attribute_v_with_intrinsic-4.c | 10 +++
>  .../target_attribute_v_with_intrinsic-5.c | 12 
>  .../target_attribute_v_with_intrinsic-6.c | 12 
>  .../target_attribute_v_with_intrinsic-7.c |  9 ++
>  .../target_attribute_v_with_intrinsic-8.c | 23 ++
>  13 files changed, 145 insertions(+), 18 deletions(-)
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-2.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-4.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-5.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-6.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
>
> diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
> index edb866d51e4..01314037461 100644
> --- a/gcc/config

Re: [PATCH v1] RISC-V: Allow RVV intrinsic when function target("arch=+v")

2024-03-25 Thread Kito Cheng 
LGTM, thanks :)

On Mon, Mar 25, 2024 at 3:42 PM  wrote:
>
> From: Pan Li 
>
> This patch would like to allow the RVV intrinsic when function is
> attributed as target("arch=+v") and build with rv64gc.  For example:
>
> vint32m1_t
> __attribute__((target("arch=+v")))
> test_1 (vint32m1_t a, vint32m1_t b, size_t vl)
> {
>   return __riscv_vadd_vv_i32m1 (a, b, vl);
> }
>
> build with -march=rv64gc -mabi=lp64d -O3, we will have asm like below:
> test_1:
>   .option push
>   .option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_\
> zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
>   vsetvli zero,a0,e32,m1,ta,ma
>   vadd.vv v8,v8,v9
>   ret
>
> The riscv_vector.h must be included when leverage intrinisc type(s) and
> API(s).  And the scope of this attribute should not excced the function
> body.  Meanwhile, to make rvv types and API(s) available for this attribute,
> include riscv_vector.h will not report error for now if v is not present
> in march.
>
> Below test are passed for this patch:
> * The riscv fully regression test.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-c.cc (riscv_pragma_intrinsic): Remove error
> when V is disabled and init the RVV types and intrinic APIs.
> * config/riscv/riscv-vector-builtins.cc (expand_builtin): Report
> error if V ext is disabled.
> * config/riscv/riscv.cc (riscv_return_value_is_vector_type_p):
> Ditto.
> (riscv_arguments_is_vector_type_p): Ditto.
> (riscv_vector_cc_function_p): Ditto.
> * config/riscv/riscv_vector.h: Remove error if V is disable.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pragma-1.c: Remove.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-1.c: 
> New test.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-2.c: 
> New test.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c: 
> New test.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-4.c: 
> New test.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-5.c: 
> New test.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-6.c: 
> New test.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c: 
> New test.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c: 
> New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/riscv-c.cc   | 18 +++
>  gcc/config/riscv/riscv-vector-builtins.cc |  5 
>  gcc/config/riscv/riscv.cc | 30 ---
>  gcc/config/riscv/riscv_vector.h   |  4 ---
>  .../gcc.target/riscv/rvv/base/pragma-1.c  |  4 ---
>  .../target_attribute_v_with_intrinsic-1.c |  5 
>  .../target_attribute_v_with_intrinsic-2.c | 18 +++
>  .../target_attribute_v_with_intrinsic-3.c | 13 
>  .../target_attribute_v_with_intrinsic-4.c | 10 +++
>  .../target_attribute_v_with_intrinsic-5.c | 12 
>  .../target_attribute_v_with_intrinsic-6.c | 12 
>  .../target_attribute_v_with_intrinsic-7.c |  9 ++
>  .../target_attribute_v_with_intrinsic-8.c | 23 ++
>  13 files changed, 145 insertions(+), 18 deletions(-)
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-1.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-2.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-4.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-5.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-6.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
>
> diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
> index edb866d51e4..01314037461 100644
> --- a/gcc/config/riscv/riscv-c.cc
> +++ b/gcc/config/riscv/riscv-c.cc
> @@ -201,14 +201,20 @@ riscv_pragma_intrinsic (cpp_reader *)
>if (strcmp (name, "vector") == 0
>|| strcmp (name, "xtheadvector") == 0)
>  {
> -  if (!TARGET_VECTOR)
> +  if (TARGET_VECTOR)
> +   riscv_vector::handle_pragma_vector ();
> +  else /* Indicates riscv_vector.h is included but v is missing in arch  
> */
> {
> - error ("%<#pragma riscv intrinsic%> option %qs needs 'V' or "
> -"'XTHEADVECTOR' extension enabled",
> -name);
> - return;
> + /* To make the

[PATCH v1] RISC-V: Allow RVV intrinsic when function target("arch=+v")

2024-03-25 Thread pan2 . li 
From: Pan Li 

This patch would like to allow the RVV intrinsic when function is
attributed as target("arch=+v") and build with rv64gc.  For example:

vint32m1_t
__attribute__((target("arch=+v")))
test_1 (vint32m1_t a, vint32m1_t b, size_t vl)
{
  return __riscv_vadd_vv_i32m1 (a, b, vl);
}

build with -march=rv64gc -mabi=lp64d -O3, we will have asm like below:
test_1:
  .option push
  .option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_\
zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
  vsetvli zero,a0,e32,m1,ta,ma
  vadd.vv v8,v8,v9
  ret

The riscv_vector.h must be included when leverage intrinisc type(s) and
API(s).  And the scope of this attribute should not excced the function
body.  Meanwhile, to make rvv types and API(s) available for this attribute,
include riscv_vector.h will not report error for now if v is not present
in march.

Below test are passed for this patch:
* The riscv fully regression test.

gcc/ChangeLog:

* config/riscv/riscv-c.cc (riscv_pragma_intrinsic): Remove error
when V is disabled and init the RVV types and intrinic APIs.
* config/riscv/riscv-vector-builtins.cc (expand_builtin): Report
error if V ext is disabled.
* config/riscv/riscv.cc (riscv_return_value_is_vector_type_p):
Ditto.
(riscv_arguments_is_vector_type_p): Ditto.
(riscv_vector_cc_function_p): Ditto.
* config/riscv/riscv_vector.h: Remove error if V is disable.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pragma-1.c: Remove.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-1.c: New 
test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-2.c: New 
test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c: New 
test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-4.c: New 
test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-5.c: New 
test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-6.c: New 
test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c: New 
test.
* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c: New 
test.

Signed-off-by: Pan Li 
---
 gcc/config/riscv/riscv-c.cc   | 18 +++
 gcc/config/riscv/riscv-vector-builtins.cc |  5 
 gcc/config/riscv/riscv.cc | 30 ---
 gcc/config/riscv/riscv_vector.h   |  4 ---
 .../gcc.target/riscv/rvv/base/pragma-1.c  |  4 ---
 .../target_attribute_v_with_intrinsic-1.c |  5 
 .../target_attribute_v_with_intrinsic-2.c | 18 +++
 .../target_attribute_v_with_intrinsic-3.c | 13 
 .../target_attribute_v_with_intrinsic-4.c | 10 +++
 .../target_attribute_v_with_intrinsic-5.c | 12 
 .../target_attribute_v_with_intrinsic-6.c | 12 
 .../target_attribute_v_with_intrinsic-7.c |  9 ++
 .../target_attribute_v_with_intrinsic-8.c | 23 ++
 13 files changed, 145 insertions(+), 18 deletions(-)
 delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-1.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-2.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-3.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-4.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-5.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-6.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c

diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index edb866d51e4..01314037461 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -201,14 +201,20 @@ riscv_pragma_intrinsic (cpp_reader *)
   if (strcmp (name, "vector") == 0
   || strcmp (name, "xtheadvector") == 0)
 {
-  if (!TARGET_VECTOR)
+  if (TARGET_VECTOR)
+   riscv_vector::handle_pragma_vector ();
+  else /* Indicates riscv_vector.h is included but v is missing in arch  */
{
- error ("%<#pragma riscv intrinsic%> option %qs needs 'V' or "
-"'XTHEADVECTOR' extension enabled",
-name);
- return;
+ /* To make the the rvv types and intrinsic API available for the
+target("arch=+v") attribute,  we need to temporally enable the
+TARGET_VECTOR, and disable it after all initialized.  */
+ target_flags |= MASK_VECTOR;
+
+ riscv_vector::init_builtins ();