RE: [PATCH v1] RISC-V: Support RVV VFCVT.X.F.V rounding mode intrinsic API
Got it, thanks!
Will start with CVT and rest frm instructions first, and then refactor.
Pan
-Original Message-
From: Kito Cheng
Sent: Wednesday, August 16, 2023 11:44 AM
To: Li, Pan2
Cc: juzhe.zh...@rivai.ai; gcc-patches ; Wang, Yanzhang
Subject: Re: [PATCH v1] RISC-V: Support RVV VFCVT.X.F.V rounding mode intrinsic
API
I would prefer to introduce an enum template argument and refactor
existing code later :)
On Wed, Aug 16, 2023 at 11:40 AM Li, Pan2 via Gcc-patches
wrote:
>
> That should work as well, but may require some changes to existing codes like
> declaration, etc.
> I am OK for both the enum or inherit, and will start with the CVT parts, then
> refactor the existing frm class.
>
> Do you have any suggestion for the decision making?
>
> Pan
>
> -Original Message-
> From: Kito Cheng
> Sent: Wednesday, August 16, 2023 11:30 AM
> To: Li, Pan2
> Cc: juzhe.zh...@rivai.ai; gcc-patches ; Wang,
> Yanzhang
> Subject: Re: [PATCH v1] RISC-V: Support RVV VFCVT.X.F.V rounding mode
> intrinsic API
>
> Or using an enum value rather than bool?
>
> I am thinking we could also simplify/remove most other frm classes,
> some practical example:
>
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> index 2074dac0f16..ace63e963a5 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> @@ -58,6 +58,11 @@ enum lst_type
> LST_INDEXED,
> };
>
> +enum frm_op_type
> +{
> + NO_FRM,
> + HAS_FRM
> +};
> /* Helper function to fold vleff and vlsegff. */
> static gimple *
> fold_fault_load (gimple_folder )
> @@ -256,41 +261,22 @@ public:
>vremu/vsadd/vsaddu/vssub/vssubu
>vfadd/vfsub/
> */
> -template
> +template
> class binop : public function_base
> {
> public:
> - rtx expand (function_expander ) const override
> + bool has_rounding_mode_operand_p () const override
> {
> -switch (e.op_info->op)
> - {
> - case OP_TYPE_vx:
> - case OP_TYPE_vf:
> - return e.use_exact_insn (code_for_pred_scalar (CODE, e.vector_mode
> ()));
> - case OP_TYPE_vv:
> - return e.use_exact_insn (code_for_pred (CODE, e.vector_mode ()));
> - default:
> - gcc_unreachable ();
> - }
> +return FRM_OP == HAS_FRM;
> }
> -};
> -
> -/* Implements below instructions for now.
> - - vfadd
> - - vfsub
> - - vfmul
> - - vfdiv
> -*/
> -template
> -class binop_frm : public function_base
> -{
> -public:
> - bool has_rounding_mode_operand_p () const override { return true; }
>
> rtx expand (function_expander ) const override
> {
> switch (e.op_info->op)
> {
> + case OP_TYPE_vx:
> + gcc_assert (FRM_OP == NO_FRM);
> + gcc_fallthrough ();
> case OP_TYPE_vf:
>return e.use_exact_insn (code_for_pred_scalar (CODE, e.vector_mode
> ()));
> case OP_TYPE_vv:
> @@ -1648,10 +1634,15 @@ public:
> };
>
> /* Implements vfcvt.x. */
> -template
> +template
> class vfcvt_x : public function_base
> {
> public:
> + bool has_rounding_mode_operand_p () const override
> + {
> +return FRM_OP == HAS_FRM;
> + }
> +
> rtx expand (function_expander ) const override
> {
> return e.use_exact_insn (code_for_pred_fcvt_x_f (UNSPEC, e.arg_mode (0)));
> @@ -2389,8 +2380,8 @@ static CONSTEXPR const viota viota_obj;
> static CONSTEXPR const vid vid_obj;
> static CONSTEXPR const binop vfadd_obj;
> static CONSTEXPR const binop vfsub_obj;
> -static CONSTEXPR const binop_frm vfadd_frm_obj;
> -static CONSTEXPR const binop_frm vfsub_frm_obj;
> +static CONSTEXPR const binop vfadd_frm_obj;
> +static CONSTEXPR const binop vfsub_frm_obj;
> static CONSTEXPR const reverse_binop vfrsub_obj;
> static CONSTEXPR const reverse_binop_frm vfrsub_frm_obj;
> static CONSTEXPR const widen_binop vfwadd_obj;
> @@ -2398,9 +2389,9 @@ static CONSTEXPR const widen_binop_frm
> vfwadd_frm_obj;
> static CONSTEXPR const widen_binop vfwsub_obj;
> static CONSTEXPR const widen_binop_frm vfwsub_frm_obj;
> static CONSTEXPR const binop vfmul_obj;
> -static CONSTEXPR const binop_frm vfmul_frm_obj;
> +static CONSTEXPR const binop vfmul_frm_obj;
> static CONSTEXPR const binop vfdiv_obj;
> -static CONSTEXPR const binop_frm vfdiv_frm_obj;
> +static CONSTEXPR const binop vfdiv_frm_obj;
> static CONSTEXPR const reverse_binop vfrdiv_obj;
> static CONSTEXPR const reverse_binop_frm vfrdiv_frm_obj;
> static CONSTEXPR const widen_binop vfwmul_obj;
Re: [PATCH v1] RISC-V: Support RVV VFCVT.X.F.V rounding mode intrinsic API
I would prefer to introduce an enum template argument and refactor
existing code later :)
On Wed, Aug 16, 2023 at 11:40 AM Li, Pan2 via Gcc-patches
wrote:
>
> That should work as well, but may require some changes to existing codes like
> declaration, etc.
> I am OK for both the enum or inherit, and will start with the CVT parts, then
> refactor the existing frm class.
>
> Do you have any suggestion for the decision making?
>
> Pan
>
> -Original Message-
> From: Kito Cheng
> Sent: Wednesday, August 16, 2023 11:30 AM
> To: Li, Pan2
> Cc: juzhe.zh...@rivai.ai; gcc-patches ; Wang,
> Yanzhang
> Subject: Re: [PATCH v1] RISC-V: Support RVV VFCVT.X.F.V rounding mode
> intrinsic API
>
> Or using an enum value rather than bool?
>
> I am thinking we could also simplify/remove most other frm classes,
> some practical example:
>
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> index 2074dac0f16..ace63e963a5 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> @@ -58,6 +58,11 @@ enum lst_type
> LST_INDEXED,
> };
>
> +enum frm_op_type
> +{
> + NO_FRM,
> + HAS_FRM
> +};
> /* Helper function to fold vleff and vlsegff. */
> static gimple *
> fold_fault_load (gimple_folder )
> @@ -256,41 +261,22 @@ public:
>vremu/vsadd/vsaddu/vssub/vssubu
>vfadd/vfsub/
> */
> -template
> +template
> class binop : public function_base
> {
> public:
> - rtx expand (function_expander ) const override
> + bool has_rounding_mode_operand_p () const override
> {
> -switch (e.op_info->op)
> - {
> - case OP_TYPE_vx:
> - case OP_TYPE_vf:
> - return e.use_exact_insn (code_for_pred_scalar (CODE, e.vector_mode
> ()));
> - case OP_TYPE_vv:
> - return e.use_exact_insn (code_for_pred (CODE, e.vector_mode ()));
> - default:
> - gcc_unreachable ();
> - }
> +return FRM_OP == HAS_FRM;
> }
> -};
> -
> -/* Implements below instructions for now.
> - - vfadd
> - - vfsub
> - - vfmul
> - - vfdiv
> -*/
> -template
> -class binop_frm : public function_base
> -{
> -public:
> - bool has_rounding_mode_operand_p () const override { return true; }
>
> rtx expand (function_expander ) const override
> {
> switch (e.op_info->op)
> {
> + case OP_TYPE_vx:
> + gcc_assert (FRM_OP == NO_FRM);
> + gcc_fallthrough ();
> case OP_TYPE_vf:
>return e.use_exact_insn (code_for_pred_scalar (CODE, e.vector_mode
> ()));
> case OP_TYPE_vv:
> @@ -1648,10 +1634,15 @@ public:
> };
>
> /* Implements vfcvt.x. */
> -template
> +template
> class vfcvt_x : public function_base
> {
> public:
> + bool has_rounding_mode_operand_p () const override
> + {
> +return FRM_OP == HAS_FRM;
> + }
> +
> rtx expand (function_expander ) const override
> {
> return e.use_exact_insn (code_for_pred_fcvt_x_f (UNSPEC, e.arg_mode (0)));
> @@ -2389,8 +2380,8 @@ static CONSTEXPR const viota viota_obj;
> static CONSTEXPR const vid vid_obj;
> static CONSTEXPR const binop vfadd_obj;
> static CONSTEXPR const binop vfsub_obj;
> -static CONSTEXPR const binop_frm vfadd_frm_obj;
> -static CONSTEXPR const binop_frm vfsub_frm_obj;
> +static CONSTEXPR const binop vfadd_frm_obj;
> +static CONSTEXPR const binop vfsub_frm_obj;
> static CONSTEXPR const reverse_binop vfrsub_obj;
> static CONSTEXPR const reverse_binop_frm vfrsub_frm_obj;
> static CONSTEXPR const widen_binop vfwadd_obj;
> @@ -2398,9 +2389,9 @@ static CONSTEXPR const widen_binop_frm
> vfwadd_frm_obj;
> static CONSTEXPR const widen_binop vfwsub_obj;
> static CONSTEXPR const widen_binop_frm vfwsub_frm_obj;
> static CONSTEXPR const binop vfmul_obj;
> -static CONSTEXPR const binop_frm vfmul_frm_obj;
> +static CONSTEXPR const binop vfmul_frm_obj;
> static CONSTEXPR const binop vfdiv_obj;
> -static CONSTEXPR const binop_frm vfdiv_frm_obj;
> +static CONSTEXPR const binop vfdiv_frm_obj;
> static CONSTEXPR const reverse_binop vfrdiv_obj;
> static CONSTEXPR const reverse_binop_frm vfrdiv_frm_obj;
> static CONSTEXPR const widen_binop vfwmul_obj;
RE: [PATCH v1] RISC-V: Support RVV VFCVT.X.F.V rounding mode intrinsic API
That should work as well, but may require some changes to existing codes like
declaration, etc.
I am OK for both the enum or inherit, and will start with the CVT parts, then
refactor the existing frm class.
Do you have any suggestion for the decision making?
Pan
-Original Message-
From: Kito Cheng
Sent: Wednesday, August 16, 2023 11:30 AM
To: Li, Pan2
Cc: juzhe.zh...@rivai.ai; gcc-patches ; Wang, Yanzhang
Subject: Re: [PATCH v1] RISC-V: Support RVV VFCVT.X.F.V rounding mode intrinsic
API
Or using an enum value rather than bool?
I am thinking we could also simplify/remove most other frm classes,
some practical example:
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 2074dac0f16..ace63e963a5 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -58,6 +58,11 @@ enum lst_type
LST_INDEXED,
};
+enum frm_op_type
+{
+ NO_FRM,
+ HAS_FRM
+};
/* Helper function to fold vleff and vlsegff. */
static gimple *
fold_fault_load (gimple_folder )
@@ -256,41 +261,22 @@ public:
vremu/vsadd/vsaddu/vssub/vssubu
vfadd/vfsub/
*/
-template
+template
class binop : public function_base
{
public:
- rtx expand (function_expander ) const override
+ bool has_rounding_mode_operand_p () const override
{
-switch (e.op_info->op)
- {
- case OP_TYPE_vx:
- case OP_TYPE_vf:
- return e.use_exact_insn (code_for_pred_scalar (CODE, e.vector_mode ()));
- case OP_TYPE_vv:
- return e.use_exact_insn (code_for_pred (CODE, e.vector_mode ()));
- default:
- gcc_unreachable ();
- }
+return FRM_OP == HAS_FRM;
}
-};
-
-/* Implements below instructions for now.
- - vfadd
- - vfsub
- - vfmul
- - vfdiv
-*/
-template
-class binop_frm : public function_base
-{
-public:
- bool has_rounding_mode_operand_p () const override { return true; }
rtx expand (function_expander ) const override
{
switch (e.op_info->op)
{
+ case OP_TYPE_vx:
+ gcc_assert (FRM_OP == NO_FRM);
+ gcc_fallthrough ();
case OP_TYPE_vf:
return e.use_exact_insn (code_for_pred_scalar (CODE, e.vector_mode ()));
case OP_TYPE_vv:
@@ -1648,10 +1634,15 @@ public:
};
/* Implements vfcvt.x. */
-template
+template
class vfcvt_x : public function_base
{
public:
+ bool has_rounding_mode_operand_p () const override
+ {
+return FRM_OP == HAS_FRM;
+ }
+
rtx expand (function_expander ) const override
{
return e.use_exact_insn (code_for_pred_fcvt_x_f (UNSPEC, e.arg_mode (0)));
@@ -2389,8 +2380,8 @@ static CONSTEXPR const viota viota_obj;
static CONSTEXPR const vid vid_obj;
static CONSTEXPR const binop vfadd_obj;
static CONSTEXPR const binop vfsub_obj;
-static CONSTEXPR const binop_frm vfadd_frm_obj;
-static CONSTEXPR const binop_frm vfsub_frm_obj;
+static CONSTEXPR const binop vfadd_frm_obj;
+static CONSTEXPR const binop vfsub_frm_obj;
static CONSTEXPR const reverse_binop vfrsub_obj;
static CONSTEXPR const reverse_binop_frm vfrsub_frm_obj;
static CONSTEXPR const widen_binop vfwadd_obj;
@@ -2398,9 +2389,9 @@ static CONSTEXPR const widen_binop_frm
vfwadd_frm_obj;
static CONSTEXPR const widen_binop vfwsub_obj;
static CONSTEXPR const widen_binop_frm vfwsub_frm_obj;
static CONSTEXPR const binop vfmul_obj;
-static CONSTEXPR const binop_frm vfmul_frm_obj;
+static CONSTEXPR const binop vfmul_frm_obj;
static CONSTEXPR const binop vfdiv_obj;
-static CONSTEXPR const binop_frm vfdiv_frm_obj;
+static CONSTEXPR const binop vfdiv_frm_obj;
static CONSTEXPR const reverse_binop vfrdiv_obj;
static CONSTEXPR const reverse_binop_frm vfrdiv_frm_obj;
static CONSTEXPR const widen_binop vfwmul_obj;
Re: [PATCH v1] RISC-V: Support RVV VFCVT.X.F.V rounding mode intrinsic API
Or using an enum value rather than bool?
I am thinking we could also simplify/remove most other frm classes,
some practical example:
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 2074dac0f16..ace63e963a5 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -58,6 +58,11 @@ enum lst_type
LST_INDEXED,
};
+enum frm_op_type
+{
+ NO_FRM,
+ HAS_FRM
+};
/* Helper function to fold vleff and vlsegff. */
static gimple *
fold_fault_load (gimple_folder )
@@ -256,41 +261,22 @@ public:
vremu/vsadd/vsaddu/vssub/vssubu
vfadd/vfsub/
*/
-template
+template
class binop : public function_base
{
public:
- rtx expand (function_expander ) const override
+ bool has_rounding_mode_operand_p () const override
{
-switch (e.op_info->op)
- {
- case OP_TYPE_vx:
- case OP_TYPE_vf:
- return e.use_exact_insn (code_for_pred_scalar (CODE, e.vector_mode ()));
- case OP_TYPE_vv:
- return e.use_exact_insn (code_for_pred (CODE, e.vector_mode ()));
- default:
- gcc_unreachable ();
- }
+return FRM_OP == HAS_FRM;
}
-};
-
-/* Implements below instructions for now.
- - vfadd
- - vfsub
- - vfmul
- - vfdiv
-*/
-template
-class binop_frm : public function_base
-{
-public:
- bool has_rounding_mode_operand_p () const override { return true; }
rtx expand (function_expander ) const override
{
switch (e.op_info->op)
{
+ case OP_TYPE_vx:
+ gcc_assert (FRM_OP == NO_FRM);
+ gcc_fallthrough ();
case OP_TYPE_vf:
return e.use_exact_insn (code_for_pred_scalar (CODE, e.vector_mode ()));
case OP_TYPE_vv:
@@ -1648,10 +1634,15 @@ public:
};
/* Implements vfcvt.x. */
-template
+template
class vfcvt_x : public function_base
{
public:
+ bool has_rounding_mode_operand_p () const override
+ {
+return FRM_OP == HAS_FRM;
+ }
+
rtx expand (function_expander ) const override
{
return e.use_exact_insn (code_for_pred_fcvt_x_f (UNSPEC, e.arg_mode (0)));
@@ -2389,8 +2380,8 @@ static CONSTEXPR const viota viota_obj;
static CONSTEXPR const vid vid_obj;
static CONSTEXPR const binop vfadd_obj;
static CONSTEXPR const binop vfsub_obj;
-static CONSTEXPR const binop_frm vfadd_frm_obj;
-static CONSTEXPR const binop_frm vfsub_frm_obj;
+static CONSTEXPR const binop vfadd_frm_obj;
+static CONSTEXPR const binop vfsub_frm_obj;
static CONSTEXPR const reverse_binop vfrsub_obj;
static CONSTEXPR const reverse_binop_frm vfrsub_frm_obj;
static CONSTEXPR const widen_binop vfwadd_obj;
@@ -2398,9 +2389,9 @@ static CONSTEXPR const widen_binop_frm
vfwadd_frm_obj;
static CONSTEXPR const widen_binop vfwsub_obj;
static CONSTEXPR const widen_binop_frm vfwsub_frm_obj;
static CONSTEXPR const binop vfmul_obj;
-static CONSTEXPR const binop_frm vfmul_frm_obj;
+static CONSTEXPR const binop vfmul_frm_obj;
static CONSTEXPR const binop vfdiv_obj;
-static CONSTEXPR const binop_frm vfdiv_frm_obj;
+static CONSTEXPR const binop vfdiv_frm_obj;
static CONSTEXPR const reverse_binop vfrdiv_obj;
static CONSTEXPR const reverse_binop_frm vfrdiv_frm_obj;
static CONSTEXPR const widen_binop vfwmul_obj;
RE: [PATCH v1] RISC-V: Support RVV VFCVT.X.F.V rounding mode intrinsic API
Thanks Kito for comments. How about leverage inherit instead of template?
AFAIK, the bool argument isn't recommended up to a point.
For example, as below to reuse the expand part.
class vfcvt_x : public function_base
{
public:
+ virtual bool has_rounding_mode_operand_p () const { return false; }
+
rtx expand (function_expander ) const override
{
return e.use_exact_insn (code_for_pred_fcvt_x_f (UNSPEC, e.arg_mode (0)));
}
};
+/* Implements below instructions for frm
+ - vfcvt_x
+*/
+template
+class vfcvt_x_frm : public vfcvt_x
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+};
Pan
-Original Message-
From: Kito Cheng
Sent: Tuesday, August 15, 2023 11:34 PM
To: juzhe.zh...@rivai.ai
Cc: Li, Pan2 ; gcc-patches ; Wang,
Yanzhang
Subject: Re: [PATCH v1] RISC-V: Support RVV VFCVT.X.F.V rounding mode intrinsic
API
Just a random idea came to my mind, maybe we could introduce one more
template argument to reduce those codes for rounding mode intrinsic
stuff?
example:
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 2074dac0f16..9cc60842a5b 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1648,10 +1648,11 @@ public:
};
/* Implements vfcvt.x. */
-template
+template
class vfcvt_x : public function_base
{
public:
+ bool has_rounding_mode_operand_p () const override { return HAS_FRM; }
rtx expand (function_expander ) const override
{
return e.use_exact_insn (code_for_pred_fcvt_x_f (UNSPEC, e.arg_mode (0)));
@@ -2451,6 +2452,7 @@ static CONSTEXPR const vmerge vfmerge_obj;
static CONSTEXPR const vmv_v vfmv_v_obj;
static CONSTEXPR const vfcvt_x vfcvt_x_obj;
static CONSTEXPR const vfcvt_x vfcvt_xu_obj;
+static CONSTEXPR const vfcvt_x vfcvt_x_frm_obj;
static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_x_obj;
static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_xu_obj;
static CONSTEXPR const vfcvt_f vfcvt_f_obj;
Re: [PATCH v1] RISC-V: Support RVV VFCVT.X.F.V rounding mode intrinsic API
Just a random idea came to my mind, maybe we could introduce one more
template argument to reduce those codes for rounding mode intrinsic
stuff?
example:
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 2074dac0f16..9cc60842a5b 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1648,10 +1648,11 @@ public:
};
/* Implements vfcvt.x. */
-template
+template
class vfcvt_x : public function_base
{
public:
+ bool has_rounding_mode_operand_p () const override { return HAS_FRM; }
rtx expand (function_expander ) const override
{
return e.use_exact_insn (code_for_pred_fcvt_x_f (UNSPEC, e.arg_mode (0)));
@@ -2451,6 +2452,7 @@ static CONSTEXPR const vmerge vfmerge_obj;
static CONSTEXPR const vmv_v vfmv_v_obj;
static CONSTEXPR const vfcvt_x vfcvt_x_obj;
static CONSTEXPR const vfcvt_x vfcvt_xu_obj;
+static CONSTEXPR const vfcvt_x vfcvt_x_frm_obj;
static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_x_obj;
static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_xu_obj;
static CONSTEXPR const vfcvt_f vfcvt_f_obj;
Re: [PATCH v1] RISC-V: Support RVV VFCVT.X.F.V rounding mode intrinsic API
For conversion API, I would prefer kito review since I am not sure about this
stuff.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-08-15 10:55
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support RVV VFCVT.X.F.V rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFCVT.X.F.V as the below samples.
* __riscv_vfcvt_x_f_v_i32m1_rm
* __riscv_vfcvt_x_f_v_i32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfcvt_x_frm): New class for frm.
(vfcvt_x_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfcvt_x_frm): New intrinsic function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-cvt-x.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 17 +++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 ++
.../riscv/rvv/base/float-point-cvt-x.c| 29 +++
4 files changed, 49 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index f2124080ef9..754a53efd3d 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -660,6 +660,21 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfcvt_x
+*/
+template
+class vfcvt_x_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ rtx expand (function_expander ) const override
+ {
+return e.use_exact_insn (code_for_pred_fcvt_x_f (UNSPEC, e.arg_mode (0)));
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2465,6 +2480,7 @@ static CONSTEXPR const vfclass vfclass_obj;
static CONSTEXPR const vmerge vfmerge_obj;
static CONSTEXPR const vmv_v vfmv_v_obj;
static CONSTEXPR const vfcvt_x vfcvt_x_obj;
+static CONSTEXPR const vfcvt_x_frm vfcvt_x_frm_obj;
static CONSTEXPR const vfcvt_x vfcvt_xu_obj;
static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_x_obj;
static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_xu_obj;
@@ -2714,6 +2730,7 @@ BASE (vfclass)
BASE (vfmerge)
BASE (vfmv_v)
BASE (vfcvt_x)
+BASE (vfcvt_x_frm)
BASE (vfcvt_xu)
BASE (vfcvt_rtz_x)
BASE (vfcvt_rtz_xu)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 2a9381eec5e..50a7d7ffb6f 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -205,6 +205,7 @@ extern const function_base *const vfclass;
extern const function_base *const vfmerge;
extern const function_base *const vfmv_v;
extern const function_base *const vfcvt_x;
+extern const function_base *const vfcvt_x_frm;
extern const function_base *const vfcvt_xu;
extern const function_base *const vfcvt_rtz_x;
extern const function_base *const vfcvt_rtz_xu;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 34def6bb82f..8b6a7cc49f3 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -445,6 +445,8 @@ DEF_RVV_FUNCTION (vfcvt_rtz_xu, alu, full_preds,
f_to_u_f_v_ops)
DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds, i_to_f_x_v_ops)
DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds, u_to_f_xu_v_ops)
+DEF_RVV_FUNCTION (vfcvt_x_frm, alu_frm, full_preds, f_to_i_f_v_ops)
+
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
DEF_RVV_FUNCTION (vfwcvt_x, alu, full_preds, f_to_wi_f_v_ops)
DEF_RVV_FUNCTION (vfwcvt_xu, alu, full_preds, f_to_wu_f_v_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c
new file mode 100644
index 000..e090f0f97e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+test_riscv_vfcvt_x_f_vv_i32m1_rm (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_x_f_v_i32m1_rm (op1, 0, vl);
+}
+
+vint32m1_t
+test_vfcvt_x_f_vv_i32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_x_f_v_i32m1_rm_m (mask, op1, 1, vl);
+}
+
+vint32m1_t
+test_riscv_vfcvt_x_f_vv_i32m1 (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_x_f_v_i32m1 (op1, vl);
+}
+
+vint32m1_t
+test_vfcvt_x_f_vv_i32m1_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_x_f_v_i32m1_m (mask, op1, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+} 4 }
} */
+/* { dg-final { scan-ass
[PATCH v1] RISC-V: Support RVV VFCVT.X.F.V rounding mode intrinsic API
From: Pan Li
This patch would like to support the rounding mode API for the
VFCVT.X.F.V as the below samples.
* __riscv_vfcvt_x_f_v_i32m1_rm
* __riscv_vfcvt_x_f_v_i32m1_rm_m
Signed-off-by: Pan Li
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(class vfcvt_x_frm): New class for frm.
(vfcvt_x_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfcvt_x_frm): New intrinsic function definition.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-cvt-x.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 17 +++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 2 ++
.../riscv/rvv/base/float-point-cvt-x.c| 29 +++
4 files changed, 49 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index f2124080ef9..754a53efd3d 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -660,6 +660,21 @@ public:
}
};
+/* Implements below instructions for frm
+ - vfcvt_x
+*/
+template
+class vfcvt_x_frm : public function_base
+{
+public:
+ bool has_rounding_mode_operand_p () const override { return true; }
+
+ rtx expand (function_expander ) const override
+ {
+return e.use_exact_insn (code_for_pred_fcvt_x_f (UNSPEC, e.arg_mode (0)));
+ }
+};
+
/* Implements vrsub. */
class vrsub : public function_base
{
@@ -2465,6 +2480,7 @@ static CONSTEXPR const vfclass vfclass_obj;
static CONSTEXPR const vmerge vfmerge_obj;
static CONSTEXPR const vmv_v vfmv_v_obj;
static CONSTEXPR const vfcvt_x vfcvt_x_obj;
+static CONSTEXPR const vfcvt_x_frm vfcvt_x_frm_obj;
static CONSTEXPR const vfcvt_x vfcvt_xu_obj;
static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_x_obj;
static CONSTEXPR const vfcvt_rtz_x vfcvt_rtz_xu_obj;
@@ -2714,6 +2730,7 @@ BASE (vfclass)
BASE (vfmerge)
BASE (vfmv_v)
BASE (vfcvt_x)
+BASE (vfcvt_x_frm)
BASE (vfcvt_xu)
BASE (vfcvt_rtz_x)
BASE (vfcvt_rtz_xu)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 2a9381eec5e..50a7d7ffb6f 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -205,6 +205,7 @@ extern const function_base *const vfclass;
extern const function_base *const vfmerge;
extern const function_base *const vfmv_v;
extern const function_base *const vfcvt_x;
+extern const function_base *const vfcvt_x_frm;
extern const function_base *const vfcvt_xu;
extern const function_base *const vfcvt_rtz_x;
extern const function_base *const vfcvt_rtz_xu;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 34def6bb82f..8b6a7cc49f3 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -445,6 +445,8 @@ DEF_RVV_FUNCTION (vfcvt_rtz_xu, alu, full_preds,
f_to_u_f_v_ops)
DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds, i_to_f_x_v_ops)
DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds, u_to_f_xu_v_ops)
+DEF_RVV_FUNCTION (vfcvt_x_frm, alu_frm, full_preds, f_to_i_f_v_ops)
+
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
DEF_RVV_FUNCTION (vfwcvt_x, alu, full_preds, f_to_wi_f_v_ops)
DEF_RVV_FUNCTION (vfwcvt_xu, alu, full_preds, f_to_wu_f_v_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c
new file mode 100644
index 000..e090f0f97e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-x.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vint32m1_t
+test_riscv_vfcvt_x_f_vv_i32m1_rm (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_x_f_v_i32m1_rm (op1, 0, vl);
+}
+
+vint32m1_t
+test_vfcvt_x_f_vv_i32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_x_f_v_i32m1_rm_m (mask, op1, 1, vl);
+}
+
+vint32m1_t
+test_riscv_vfcvt_x_f_vv_i32m1 (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_x_f_v_i32m1 (op1, vl);
+}
+
+vint32m1_t
+test_vfcvt_x_f_vv_i32m1_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_x_f_v_i32m1_m (mask, op1, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+} 4 }
} */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
--
2.34.1
