From: Pan Li
After we support branchless __builtin_add_overflow unsigned SAT_ADD from
the middle end. Add more tests case to cover the functionarlities.
The below test suites are passed.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_arith.h: Add __builtin_add_overflow test
macro.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c: New test.
* gcc.target/riscv/sat_u_add-5.c: New test.
* gcc.target/riscv/sat_u_add-6.c: New test.
* gcc.target/riscv/sat_u_add-7.c: New test.
* gcc.target/riscv/sat_u_add-8.c: New test.
* gcc.target/riscv/sat_u_add-run-5.c: New test.
* gcc.target/riscv/sat_u_add-run-6.c: New test.
* gcc.target/riscv/sat_u_add-run-7.c: New test.
* gcc.target/riscv/sat_u_add-run-8.c: New test.
Signed-off-by: Pan Li
---
.../riscv/rvv/autovec/binop/vec_sat_u_add-5.c | 19 +
.../riscv/rvv/autovec/binop/vec_sat_u_add-6.c | 20 +
.../riscv/rvv/autovec/binop/vec_sat_u_add-7.c | 20 +
.../riscv/rvv/autovec/binop/vec_sat_u_add-8.c | 20 +
.../rvv/autovec/binop/vec_sat_u_add-run-5.c | 75 +++
.../rvv/autovec/binop/vec_sat_u_add-run-6.c | 75 +++
.../rvv/autovec/binop/vec_sat_u_add-run-7.c | 75 +++
.../rvv/autovec/binop/vec_sat_u_add-run-8.c | 75 +++
gcc/testsuite/gcc.target/riscv/sat_arith.h| 27 +++
gcc/testsuite/gcc.target/riscv/sat_u_add-5.c | 19 +
gcc/testsuite/gcc.target/riscv/sat_u_add-6.c | 21 ++
gcc/testsuite/gcc.target/riscv/sat_u_add-7.c | 18 +
gcc/testsuite/gcc.target/riscv/sat_u_add-8.c | 17 +
.../gcc.target/riscv/sat_u_add-run-5.c| 25 +++
.../gcc.target/riscv/sat_u_add-run-6.c| 25 +++
.../gcc.target/riscv/sat_u_add-run-7.c| 25 +++
.../gcc.target/riscv/sat_u_add-run-8.c| 25 +++
17 files changed, 581 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-8.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-7.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-8.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
new file mode 100644
index 000..47d83b0927d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "../../../sat_arith.h"
+
+/*
+** vec_sat_u_add_uint8_t_fmt_2:
+** ...
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
+** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+** ...
+*/
+DEF_VEC_SAT_U_ADD_FMT_2(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c
new file mode 100644
index 000..b5d612dba21
--- /dev/null
+++
