From: Christoph Müllner <christoph.muell...@vrull.eu> This series introduces strlen/strcmp/strncmp inline expansion for Zbb/XTheadBb.
In the last months, glibc as well as the Linux kernel merged changes for optimized string processing for RISC-V. The instruction, which enables optimized string routines is Zbb's orc.b (or T-Head's th.tstnbz) instruction. This patch attempts to add optimized string processing to GCC with the following properties: * strlen: inline a loop if the string is xlen-aligned * strcmp/strncmp: inline a peeled comparison loop sequence if both strings are xlen-aligned I've already posted the idea in a previous series last November (therefore, this series is called 'v2'): * https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605996.html * https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605998.html Back then, there were a couple of comments, which have been addressed, but the str(n)cmp patch has been restructured to make the code easier to digest. In total the following changes are made: * Address Jeff's comments for the strlen patch * Change str(n)cmp flags according to Kito's comments * Ensure that all flags are documented * Break str(n)cmp expansion into several functions * Add support for XTheadBb's th.tstnbz I have not introduced "-minline-str[n]cmp=[bitmanip|vector|auto]" or "-mstringop-strategy=alg" because we only have one bitmanip/scalar expansion. But it is possible to add this in the future (or not and decide based on mtune). By default all optimizations are disabled, so there should be no risk of regressions. Testing was done using the following strategy: * Enablement/flag tests are part of the patches * Correctness was tested using qemu-user with glibc's string tests compiled for: ** rv64gc (baseline) QEMU_CPU=rv64 ** rv64gc_zbb (limit=64) QEMU_CPU=rv64,zbb=false (must fail) ** rv64gc_zbb (limit=64) QEMU_CPU=rv64,zbb=true ** rv64gc_zbb (limit=32) QEMU_CPU=rv64,zbb=true ** rv64gc_xtheadbb (limit=64) QEMU_CPU=rv64 (must fail) ** rv64gc_xtheadbb (limit=64) QEMU_CPU=thead-c906 ** rv64gc_xtheadbb (limit=8) QEMU_CPU=thead-c906 ** rv32gc_zbb (limit=64) QEMU_CPU=rv32,zbb=true * SPEC CPU 2017 intrate base/peak with LTO Christoph Müllner (2): riscv: Add support for strlen inline expansion riscv: Add support for str(n)cmp inline expansion gcc/config.gcc | 3 +- gcc/config/riscv/bitmanip.md | 2 +- gcc/config/riscv/riscv-protos.h | 4 + gcc/config/riscv/riscv-string.cc | 594 ++++++++++++++++++ gcc/config/riscv/riscv.md | 72 ++- gcc/config/riscv/riscv.opt | 16 + gcc/config/riscv/t-riscv | 6 + gcc/config/riscv/thead.md | 9 +- gcc/doc/invoke.texi | 29 +- gcc/emit-rtl.cc | 24 + gcc/rtl.h | 2 + .../gcc.target/riscv/xtheadbb-strcmp.c | 57 ++ .../riscv/xtheadbb-strlen-unaligned.c | 14 + .../gcc.target/riscv/xtheadbb-strlen.c | 19 + .../gcc.target/riscv/zbb-strcmp-disabled-2.c | 38 ++ .../gcc.target/riscv/zbb-strcmp-disabled.c | 38 ++ .../gcc.target/riscv/zbb-strcmp-limit.c | 57 ++ .../gcc.target/riscv/zbb-strcmp-unaligned.c | 38 ++ gcc/testsuite/gcc.target/riscv/zbb-strcmp.c | 57 ++ .../gcc.target/riscv/zbb-strlen-disabled-2.c | 15 + .../gcc.target/riscv/zbb-strlen-disabled.c | 15 + .../gcc.target/riscv/zbb-strlen-unaligned.c | 14 + gcc/testsuite/gcc.target/riscv/zbb-strlen.c | 19 + 23 files changed, 1137 insertions(+), 5 deletions(-) create mode 100644 gcc/config/riscv/riscv-string.cc create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-strcmp.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-strlen-unaligned.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-strlen.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-strcmp-disabled-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-strcmp-disabled.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-strcmp-limit.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-strcmp-unaligned.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-strcmp.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-strlen-disabled-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-strlen-disabled.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-strlen-unaligned.c create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-strlen.c -- 2.41.0
