Re: [PATCH v2 1/2] riscv: thead: Add support for the XTheadMemIdx ISA extension
On Sun, Oct 29, 2023 at 10:44 PM Jeff Law wrote:
>
>
>
> On 10/20/23 03:53, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > The XTheadMemIdx ISA extension provides a additional load and store
> > instructions with new addressing modes.
> >
> > The following memory accesses types are supported:
> > * load: b,bu,h,hu,w,wu,d
> > * store: b,h,w,d
> >
> > The following addressing modes are supported:
> > * immediate offset with PRE_MODIFY or POST_MODIFY (22 instructions):
> >l.ia, l.ib, s.ia, s.ib
> > * register offset with additional immediate offset (11 instructions):
> >lr, sr
> > * zero-extended register offset with additional immediate offset
> >(11 instructions): lur, sur
> >
> > The RISC-V base ISA does not support index registers, so the changes
> > are kept separate from the RISC-V standard support as much as possible.
> >
> > To combine the shift/multiply instructions into the memory access
> > instructions, this patch comes with a few insn_and_split optimizations
> > that allow the combiner to do this task.
> >
> > Handling the different cases of extensions results in a couple of INSNs
> > that look redundant on first view, but they are just the equivalence
> > of what we already have for Zbb as well. The only difference is, that
> > we have much more load instructions.
> >
> > We already have a constraint with the name 'th_f_fmv', therefore,
> > the new constraints follow this pattern and have the same length
> > as required ('th_m_mia', 'th_m_mib', 'th_m_mir', 'th_m_miu').
> >
> > The added tests ensure that this feature won't regress without notice.
> > Testing: GCC regression test suite, GCC bootstrap build, and
> > SPEC CPU 2017 intrate (base) on C920.
> >
> > Signed-off-by: Christoph Müllner
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/constraints.md (th_m_mia): New constraint.
> > (th_m_mib): Likewise.
> > (th_m_mir): Likewise.
> > (th_m_miu): Likewise.
> > * config/riscv/riscv-protos.h (enum riscv_address_type):
> > Add new address types ADDRESS_REG_REG, ADDRESS_REG_UREG,
> > and ADDRESS_REG_WB and their documentation.
> > (struct riscv_address_info): Add new field 'shift' and
> > document the field usage for the new address types.
> > (riscv_valid_base_register_p): New prototype.
> > (th_memidx_legitimate_modify_p): Likewise.
> > (th_memidx_legitimate_index_p): Likewise.
> > (th_classify_address): Likewise.
> > (th_output_move): Likewise.
> > (th_print_operand_address): Likewise.
> > * config/riscv/riscv.cc (riscv_index_reg_class):
> > Return GR_REGS for XTheadMemIdx.
> > (riscv_regno_ok_for_index_p): Add support for XTheadMemIdx.
> > (riscv_classify_address): Call th_classify_address() on top.
> > (riscv_output_move): Call th_output_move() on top.
> > (riscv_print_operand_address): Call th_print_operand_address()
> > on top.
> > * config/riscv/riscv.h (HAVE_POST_MODIFY_DISP): New macro.
> > (HAVE_PRE_MODIFY_DISP): Likewise.
> > * config/riscv/riscv.md (zero_extendqi2): Disable
> > for XTheadMemIdx.
> > (*zero_extendqi2_internal): Convert to expand,
> > create INSN with same name and disable it for XTheadMemIdx.
> > (extendsidi2): Likewise.
> > (*extendsidi2_internal): Disable for XTheadMemIdx.
> > * config/riscv/thead.cc (valid_signed_immediate): New helper
> > function.
> > (th_memidx_classify_address_modify): New function.
> > (th_memidx_legitimate_modify_p): Likewise.
> > (th_memidx_output_modify): Likewise.
> > (is_memidx_mode): Likewise.
> > (th_memidx_classify_address_index): Likewise.
> > (th_memidx_legitimate_index_p): Likewise.
> > (th_memidx_output_index): Likewise.
> > (th_classify_address): Likewise.
> > (th_output_move): Likewise.
> > (th_print_operand_address): Likewise.
> > * config/riscv/thead.md (*th_memidx_operand): New splitter.
> > (*th_memidx_zero_extendqi2): New INSN.
> > (*th_memidx_extendsidi2): Likewise.
> > (*th_memidx_zero_extendsidi2): Likewise.
> > (*th_memidx_zero_extendhi2): Likewise.
> > (*th_memidx_extend2): Likewise.
> > (*th_memidx_bb_zero_extendsidi2): Likewise.
> > (*th_memidx_bb_zero_extendhi2): Likewise.
> > (*th_memidx_bb_extendhi2): Likewise.
> > (*th_memidx_bb_extendqi2): Likewise.
> > (TH_M_ANYI): New mode iterator.
> > (TH_M_NOEXTI): Likewise.
> > (*th_memidx_I_a): New combiner optimization.
> > (*th_memidx_I_b): Likewise.
> > (*th_memidx_I_c): Likewise.
> > (*th_memidx_US_a): Likewise.
> > (*th_memidx_US_b): Likewise.
> > (*th_memidx_US_c): Likewise.
> > (*th_memidx_UZ_a): Likewise.
> > (*th_memidx_UZ_b): Likewise.
> > (*th_memidx_UZ_c): Likewise.
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/xtheadmemidx-helpers.h: New test.
Re: [PATCH v2 1/2] riscv: thead: Add support for the XTheadMemIdx ISA extension
On 10/20/23 03:53, Christoph Muellner wrote:
From: Christoph Müllner
The XTheadMemIdx ISA extension provides a additional load and store
instructions with new addressing modes.
The following memory accesses types are supported:
* load: b,bu,h,hu,w,wu,d
* store: b,h,w,d
The following addressing modes are supported:
* immediate offset with PRE_MODIFY or POST_MODIFY (22 instructions):
l.ia, l.ib, s.ia, s.ib
* register offset with additional immediate offset (11 instructions):
lr, sr
* zero-extended register offset with additional immediate offset
(11 instructions): lur, sur
The RISC-V base ISA does not support index registers, so the changes
are kept separate from the RISC-V standard support as much as possible.
To combine the shift/multiply instructions into the memory access
instructions, this patch comes with a few insn_and_split optimizations
that allow the combiner to do this task.
Handling the different cases of extensions results in a couple of INSNs
that look redundant on first view, but they are just the equivalence
of what we already have for Zbb as well. The only difference is, that
we have much more load instructions.
We already have a constraint with the name 'th_f_fmv', therefore,
the new constraints follow this pattern and have the same length
as required ('th_m_mia', 'th_m_mib', 'th_m_mir', 'th_m_miu').
The added tests ensure that this feature won't regress without notice.
Testing: GCC regression test suite, GCC bootstrap build, and
SPEC CPU 2017 intrate (base) on C920.
Signed-off-by: Christoph Müllner
gcc/ChangeLog:
* config/riscv/constraints.md (th_m_mia): New constraint.
(th_m_mib): Likewise.
(th_m_mir): Likewise.
(th_m_miu): Likewise.
* config/riscv/riscv-protos.h (enum riscv_address_type):
Add new address types ADDRESS_REG_REG, ADDRESS_REG_UREG,
and ADDRESS_REG_WB and their documentation.
(struct riscv_address_info): Add new field 'shift' and
document the field usage for the new address types.
(riscv_valid_base_register_p): New prototype.
(th_memidx_legitimate_modify_p): Likewise.
(th_memidx_legitimate_index_p): Likewise.
(th_classify_address): Likewise.
(th_output_move): Likewise.
(th_print_operand_address): Likewise.
* config/riscv/riscv.cc (riscv_index_reg_class):
Return GR_REGS for XTheadMemIdx.
(riscv_regno_ok_for_index_p): Add support for XTheadMemIdx.
(riscv_classify_address): Call th_classify_address() on top.
(riscv_output_move): Call th_output_move() on top.
(riscv_print_operand_address): Call th_print_operand_address()
on top.
* config/riscv/riscv.h (HAVE_POST_MODIFY_DISP): New macro.
(HAVE_PRE_MODIFY_DISP): Likewise.
* config/riscv/riscv.md (zero_extendqi2): Disable
for XTheadMemIdx.
(*zero_extendqi2_internal): Convert to expand,
create INSN with same name and disable it for XTheadMemIdx.
(extendsidi2): Likewise.
(*extendsidi2_internal): Disable for XTheadMemIdx.
* config/riscv/thead.cc (valid_signed_immediate): New helper
function.
(th_memidx_classify_address_modify): New function.
(th_memidx_legitimate_modify_p): Likewise.
(th_memidx_output_modify): Likewise.
(is_memidx_mode): Likewise.
(th_memidx_classify_address_index): Likewise.
(th_memidx_legitimate_index_p): Likewise.
(th_memidx_output_index): Likewise.
(th_classify_address): Likewise.
(th_output_move): Likewise.
(th_print_operand_address): Likewise.
* config/riscv/thead.md (*th_memidx_operand): New splitter.
(*th_memidx_zero_extendqi2): New INSN.
(*th_memidx_extendsidi2): Likewise.
(*th_memidx_zero_extendsidi2): Likewise.
(*th_memidx_zero_extendhi2): Likewise.
(*th_memidx_extend2): Likewise.
(*th_memidx_bb_zero_extendsidi2): Likewise.
(*th_memidx_bb_zero_extendhi2): Likewise.
(*th_memidx_bb_extendhi2): Likewise.
(*th_memidx_bb_extendqi2): Likewise.
(TH_M_ANYI): New mode iterator.
(TH_M_NOEXTI): Likewise.
(*th_memidx_I_a): New combiner optimization.
(*th_memidx_I_b): Likewise.
(*th_memidx_I_c): Likewise.
(*th_memidx_US_a): Likewise.
(*th_memidx_US_b): Likewise.
(*th_memidx_US_c): Likewise.
(*th_memidx_UZ_a): Likewise.
(*th_memidx_UZ_b): Likewise.
(*th_memidx_UZ_c): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadmemidx-helpers.h: New test.
* gcc.target/riscv/xtheadmemidx-index-update.c: New test.
* gcc.target/riscv/xtheadmemidx-index-xtheadbb-update.c: New test.
* gcc.target/riscv/xtheadmemidx-index-xtheadbb.c: New test.
* gcc.target/riscv/xtheadmemidx-index.c: New test.
* gcc.target/riscv/xtheadmemidx-modify-xtheadbb.c: New test.
[PATCH v2 1/2] riscv: thead: Add support for the XTheadMemIdx ISA extension
From: Christoph Müllner
The XTheadMemIdx ISA extension provides a additional load and store
instructions with new addressing modes.
The following memory accesses types are supported:
* load: b,bu,h,hu,w,wu,d
* store: b,h,w,d
The following addressing modes are supported:
* immediate offset with PRE_MODIFY or POST_MODIFY (22 instructions):
l.ia, l.ib, s.ia, s.ib
* register offset with additional immediate offset (11 instructions):
lr, sr
* zero-extended register offset with additional immediate offset
(11 instructions): lur, sur
The RISC-V base ISA does not support index registers, so the changes
are kept separate from the RISC-V standard support as much as possible.
To combine the shift/multiply instructions into the memory access
instructions, this patch comes with a few insn_and_split optimizations
that allow the combiner to do this task.
Handling the different cases of extensions results in a couple of INSNs
that look redundant on first view, but they are just the equivalence
of what we already have for Zbb as well. The only difference is, that
we have much more load instructions.
We already have a constraint with the name 'th_f_fmv', therefore,
the new constraints follow this pattern and have the same length
as required ('th_m_mia', 'th_m_mib', 'th_m_mir', 'th_m_miu').
The added tests ensure that this feature won't regress without notice.
Testing: GCC regression test suite, GCC bootstrap build, and
SPEC CPU 2017 intrate (base) on C920.
Signed-off-by: Christoph Müllner
gcc/ChangeLog:
* config/riscv/constraints.md (th_m_mia): New constraint.
(th_m_mib): Likewise.
(th_m_mir): Likewise.
(th_m_miu): Likewise.
* config/riscv/riscv-protos.h (enum riscv_address_type):
Add new address types ADDRESS_REG_REG, ADDRESS_REG_UREG,
and ADDRESS_REG_WB and their documentation.
(struct riscv_address_info): Add new field 'shift' and
document the field usage for the new address types.
(riscv_valid_base_register_p): New prototype.
(th_memidx_legitimate_modify_p): Likewise.
(th_memidx_legitimate_index_p): Likewise.
(th_classify_address): Likewise.
(th_output_move): Likewise.
(th_print_operand_address): Likewise.
* config/riscv/riscv.cc (riscv_index_reg_class):
Return GR_REGS for XTheadMemIdx.
(riscv_regno_ok_for_index_p): Add support for XTheadMemIdx.
(riscv_classify_address): Call th_classify_address() on top.
(riscv_output_move): Call th_output_move() on top.
(riscv_print_operand_address): Call th_print_operand_address()
on top.
* config/riscv/riscv.h (HAVE_POST_MODIFY_DISP): New macro.
(HAVE_PRE_MODIFY_DISP): Likewise.
* config/riscv/riscv.md (zero_extendqi2): Disable
for XTheadMemIdx.
(*zero_extendqi2_internal): Convert to expand,
create INSN with same name and disable it for XTheadMemIdx.
(extendsidi2): Likewise.
(*extendsidi2_internal): Disable for XTheadMemIdx.
* config/riscv/thead.cc (valid_signed_immediate): New helper
function.
(th_memidx_classify_address_modify): New function.
(th_memidx_legitimate_modify_p): Likewise.
(th_memidx_output_modify): Likewise.
(is_memidx_mode): Likewise.
(th_memidx_classify_address_index): Likewise.
(th_memidx_legitimate_index_p): Likewise.
(th_memidx_output_index): Likewise.
(th_classify_address): Likewise.
(th_output_move): Likewise.
(th_print_operand_address): Likewise.
* config/riscv/thead.md (*th_memidx_operand): New splitter.
(*th_memidx_zero_extendqi2): New INSN.
(*th_memidx_extendsidi2): Likewise.
(*th_memidx_zero_extendsidi2): Likewise.
(*th_memidx_zero_extendhi2): Likewise.
(*th_memidx_extend2): Likewise.
(*th_memidx_bb_zero_extendsidi2): Likewise.
(*th_memidx_bb_zero_extendhi2): Likewise.
(*th_memidx_bb_extendhi2): Likewise.
(*th_memidx_bb_extendqi2): Likewise.
(TH_M_ANYI): New mode iterator.
(TH_M_NOEXTI): Likewise.
(*th_memidx_I_a): New combiner optimization.
(*th_memidx_I_b): Likewise.
(*th_memidx_I_c): Likewise.
(*th_memidx_US_a): Likewise.
(*th_memidx_US_b): Likewise.
(*th_memidx_US_c): Likewise.
(*th_memidx_UZ_a): Likewise.
(*th_memidx_UZ_b): Likewise.
(*th_memidx_UZ_c): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadmemidx-helpers.h: New test.
* gcc.target/riscv/xtheadmemidx-index-update.c: New test.
* gcc.target/riscv/xtheadmemidx-index-xtheadbb-update.c: New test.
* gcc.target/riscv/xtheadmemidx-index-xtheadbb.c: New test.
* gcc.target/riscv/xtheadmemidx-index.c: New test.
* gcc.target/riscv/xtheadmemidx-modify-xtheadbb.c: New test.
* gcc.target/riscv/xtheadmemidx-modify.c: New test.
