Re: [PATCH v2 2/5] RISC-V: Add Types for Un-Typed zc Instructions

2023-09-08 Thread Jeff Law via Gcc-patches 




On 9/8/23 12:16, Edwin Lu wrote:

This patch adds types to the untyped zc instructions. Creates a new
types "pushpop" and "mvpair" for now

gcc/ChangeLog:

* config/riscv/riscv.md: Add "csr" type
* config/riscv/zc.md: Update types

OK.

Note that once we finish this exercise, making sure any new types that 
have been created are handled by the existing scheduling descriptions 
would be good follow-up.


jeff

[PATCH v2 2/5] RISC-V: Add Types for Un-Typed zc Instructions

2023-09-08 Thread Edwin Lu 
This patch adds types to the untyped zc instructions. Creates a new
types "pushpop" and "mvpair" for now

gcc/ChangeLog:

* config/riscv/riscv.md: Add "csr" type
* config/riscv/zc.md: Update types

Signed-off-by: Edwin Lu 
---
Changes in V2:
  - Change "csr" type to "pushpop" and "mvpair"
---
 gcc/config/riscv/riscv.md |   6 ++-
 gcc/config/riscv/zc.md| 102 +++---
 2 files changed, 56 insertions(+), 52 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index b630b51ee50..a6046c17fc3 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -316,6 +316,8 @@ (define_attr "ext_enabled" "no,yes"
 ;; condmoveconditional moves
 ;; cbocache block instructions
 ;; crypto cryptography instructions
+;; pushpopzc push and pop instructions
+;; mvpairzc move pair instructions
 ;; Classification of RVV instructions which will be added to each RVV .md 
pattern and used by scheduler.
 ;; rdvlenb vector byte length vlenb csrr read
 ;; rdvlvector length vl csrr read
@@ -425,8 +427,8 @@ (define_attr "type"
mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip,
rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
-   atomic,condmove,cbo,crypto,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
-   vlde,vste,vldm,vstm,vlds,vsts,
+   atomic,condmove,cbo,crypto,pushpop,mvpair,rdvlenb,rdvl,wrvxrm,wrfrm,
+   rdfrm,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
vldux,vldox,vstux,vstox,vldff,vldr,vstr,

vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,
vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,
diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md
index 77b28adde95..18b3c30c342 100644
--- a/gcc/config/riscv/zc.md
+++ b/gcc/config/riscv/zc.md
@@ -27,7 +27,7 @@ (define_insn "@gpr_multi_pop_up_to_ra_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra}, %0"
-)
+[(set_attr "type" "pushpop")])
 
 (define_insn "@gpr_multi_pop_up_to_s0_"
   [(set (reg:X SP_REGNUM)
@@ -41,7 +41,7 @@ (define_insn "@gpr_multi_pop_up_to_s0_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0}, %0"
-)
+[(set_attr "type" "pushpop")])
 
 (define_insn "@gpr_multi_pop_up_to_s1_"
   [(set (reg:X SP_REGNUM)
@@ -58,7 +58,7 @@ (define_insn "@gpr_multi_pop_up_to_s1_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s1}, %0"
-)
+[(set_attr "type" "pushpop")])
 
 (define_insn "@gpr_multi_pop_up_to_s2_"
   [(set (reg:X SP_REGNUM)
@@ -78,7 +78,7 @@ (define_insn "@gpr_multi_pop_up_to_s2_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s2}, %0"
-)
+[(set_attr "type" "pushpop")])
 
 (define_insn "@gpr_multi_pop_up_to_s3_"
   [(set (reg:X SP_REGNUM)
@@ -101,7 +101,7 @@ (define_insn "@gpr_multi_pop_up_to_s3_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s3}, %0"
-)
+[(set_attr "type" "pushpop")])
 
 (define_insn "@gpr_multi_pop_up_to_s4_"
   [(set (reg:X SP_REGNUM)
@@ -127,7 +127,7 @@ (define_insn "@gpr_multi_pop_up_to_s4_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s4}, %0"
-)
+[(set_attr "type" "pushpop")])
 
 (define_insn "@gpr_multi_pop_up_to_s5_"
   [(set (reg:X SP_REGNUM)
@@ -156,7 +156,7 @@ (define_insn "@gpr_multi_pop_up_to_s5_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s5}, %0"
-)
+[(set_attr "type" "pushpop")])
 
 (define_insn "@gpr_multi_pop_up_to_s6_"
   [(set (reg:X SP_REGNUM)
@@ -188,7 +188,7 @@ (define_insn "@gpr_multi_pop_up_to_s6_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s6}, %0"
-)
+[(set_attr "type" "pushpop")])
 
 (define_insn "@gpr_multi_pop_up_to_s7_"
   [(set (reg:X SP_REGNUM)
@@ -223,7 +223,7 @@ (define_insn "@gpr_multi_pop_up_to_s7_"
   (const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s7}, %0"
-)
+[(set_attr "type" "pushpop")])
 
 (define_insn "@gpr_multi_pop_up_to_s8_"
   [(set (reg:X SP_REGNUM)
@@ -261,7 +261,7 @@ (define_insn "@gpr_multi_pop_up_to_s8_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s8}, %0"
-)
+[(set_attr "type" "pushpop")])
 
 (define_insn "@gpr_multi_pop_up_to_s9_"
   [(set (reg:X SP_REGNUM)
@@ -302,7 +302,7 @@ (define_insn "@gpr_multi_pop_up_to_s9_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s9}, %0"
-)
+[(set_attr "type" "pushpop")])
 
 (define_insn "@gpr_multi_pop_up_to_s11_"
   [(set (reg:X SP_REGNUM)
@@ -349,7 +349,7 @@ (define_insn "@gpr_multi_pop_up_to_s11_"
(const_int ]
   "TARGET_ZCMP"
   "cm.pop  {ra, s0-s11}, %0"
-)
+[(set_attr "type" "pushpop")])
 
 (define_insn "@gpr_multi_popret_up_to_ra_"
   [(set (reg:X SP_REGNUM)
@@ -362,7 +362,7 @@ (define_insn "@gpr_m