Re: [PATCH v2 3/3] RISC-V: Add support for XCVbi extension in CV32E40P

[Patrick O'Neill]

Hi Mary,

GCC tip-of-tree with this patch series applied fails to build glibc with:
--with-arch=rv32imac --with-abi=ilp32
--with-arch=rv32imafdc --with-abi=ilp32d

Failing command:
./bin/riscv32-unknown-elf-gcc 
-B/scratch/tc-testing/tc-nov-13-zcvbi-series/build/build-newlib/riscv32-unknown-elf/newlib/ 
-isystem 
/scratch/tc-testing/tc-nov-13-zcvbi-series/build/build-newlib/riscv32-unknown-elf/newlib/targ-include 
-isystem 
/scratch/tc-testing/tc-nov-13-zcvbi-series/newlib/newlib/libc/include 
-B/scratch/tc-testing/tc-nov-13-zcvbi-series/build/build-newlib/riscv32-unknown-elf/libgloss/riscv32 
-L/scratch/tc-testing/tc-nov-13-zcvbi-series/build/build-newlib/riscv32-unknown-elf/libgloss/libnosys 
-L/scratch/tc-testing/tc-nov-13-zcvbi-series/newlib/libgloss/riscv32 
-DPACKAGE_NAME=\"newlib\" -DPACKAGE_TARNAME=\"newlib\" 
-DPACKAGE_VERSION=\"4.1.0\" -DPACKAGE_STRING=\"newlib\ 4.1.0\" 
-DPACKAGE_BUGREPORT=\"\" -DPACKAGE_URL=\"\" -I. 
-I/scratch/tc-testing/tc-nov-13-zcvbi-series/build/../newlib/newlib/libc/time 
-fno-builtin -DHAVE_NANOSLEEP  -O2 -D_POSIX_MODE -ffunction-sections 
-fdata-sections    -mcmodel=medlow -c -o lib_a-mktime.o `test -f 
'mktime.c' || echo 
'/scratch/tc-testing/tc-nov-13-zcvbi-series/build/../newlib/newlib/libc/time/'`mktime.c

during RTL pass: combine
/scratch/tc-testing/tc-nov-13-zcvbi-series/build/../newlib/newlib/libc/time/mktime.c: 
In function 'validate_structure':
/scratch/tc-testing/tc-nov-13-zcvbi-series/build/../newlib/newlib/libc/time/mktime.c:148:1: 
internal compiler error: Segmentation fault

  148 | }
  | ^
0x1276843 crash_signal
    ../../../gcc/gcc/toplev.cc:316
0x2136c93 recog_1349
    ../../../gcc/gcc/config/riscv/thead.md:438
0x21dcab5 recog_for_combine_1
    ../../../gcc/gcc/combine.cc:11382
0x21e12ae recog_for_combine
    ../../../gcc/gcc/combine.cc:11652
0x21f594a try_combine
    ../../../gcc/gcc/combine.cc:3867
0x21f8159 combine_instructions
    ../../../gcc/gcc/combine.cc:1285
0x21f8159 rest_of_handle_combine
    ../../../gcc/gcc/combine.cc:15080
0x21f8159 execute
    ../../../gcc/gcc/combine.cc:15124
Please submit a full bug report, with preprocessed source (by using 
-freport-bug).

Please include the complete backtrace with any bug report.
See  for instructions.

Creduced testcase:
./bin/riscv32-unknown-elf-gcc -O1 mktime.c -freport-bug
int a, b;
void c() { a = b % 7; }

during RTL pass: combine
mktime.c: In function 'c':
mktime.c:2:23: internal compiler error: Segmentation fault
    2 | void c() { a = b % 7; }
  |   ^
0x1276843 crash_signal
    ../../../gcc/gcc/toplev.cc:316
0x2136c93 recog_1349
    ../../../gcc/gcc/config/riscv/thead.md:438
0x21dcab5 recog_for_combine_1
    ../../../gcc/gcc/combine.cc:11382
0x21e12ae recog_for_combine
    ../../../gcc/gcc/combine.cc:11652
0x21f594a try_combine
    ../../../gcc/gcc/combine.cc:3867
0x21f8159 combine_instructions
    ../../../gcc/gcc/combine.cc:1285
0x21f8159 rest_of_handle_combine
    ../../../gcc/gcc/combine.cc:15080
0x21f8159 execute
    ../../../gcc/gcc/combine.cc:15124
Please submit a full bug report, with preprocessed source.
Please include the complete backtrace with any bug report.
See  for instructions.
Preprocessed source stored into /tmp/ccJL816S.out file, please attach 
this to your bugreport.


I've attached the -freport-bug output to this email.

Thanks,
Patrick

glibc: a704fd9a133bfb10510e18702f48a6a9c88dbbd5
gcc base hash: 2020bce38cf2e02cbd1097faa8f1fd6586364a7e

On 11/13/23 05:35, Mary Bennett wrote:

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
   Mary Bennett 
   Nandni Jamnadas 
   Pietra Ferreira 
   Charlie Keaney
   Jessica Mills
   Craig Blackmore 
   Simon Cook 
   Jeremy Bennett 
   Helene Chelin 

gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Create XCVbi extension
  support.
* config/riscv/riscv.opt: Likewise.
* config/riscv/corev.md: Implement cv_branch pattern
  for cv.beqimm and cv.bneimm.
* config/riscv/riscv.md: Change pattern priority so corev.md
  patterns run before riscv.md patterns.
* config/riscv/constraints.md: Implement constraints
  cv_bi_s5 - signed 5-bit immediate.
* config/riscv/predicates.md: Implement predicate
  const_int5s_operand - signed 5 bit immediate.
* doc/sourcebuild.texi: Add XCVbi documentation.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
* lib/target-supports.exp: Add proc for XCVbi.
---
  gcc/common/config/riscv/riscv-common.cc   |  2 +
  gcc/config/riscv/constraints.md   |  6 +++
  

Re: [PATCH v2 3/3] RISC-V: Add support for XCVbi extension in CV32E40P

[Kito Cheng]

I would prefer you suppress those patterns in riscv.cc rather than
adjust the including order, T-Head extension goes that way too, so I
would prefer to keep it using a consistent way.

you can search !TARGET_XTHEAD in riscv.md


On Mon, Nov 13, 2023 at 9:36 PM Mary Bennett  wrote:
>
> Spec: 
> github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md
>
> Contributors:
>   Mary Bennett 
>   Nandni Jamnadas 
>   Pietra Ferreira 
>   Charlie Keaney
>   Jessica Mills
>   Craig Blackmore 
>   Simon Cook 
>   Jeremy Bennett 
>   Helene Chelin 
>
> gcc/ChangeLog:
> * common/config/riscv/riscv-common.cc: Create XCVbi extension
>   support.
> * config/riscv/riscv.opt: Likewise.
> * config/riscv/corev.md: Implement cv_branch pattern
>   for cv.beqimm and cv.bneimm.
> * config/riscv/riscv.md: Change pattern priority so corev.md
>   patterns run before riscv.md patterns.
> * config/riscv/constraints.md: Implement constraints
>   cv_bi_s5 - signed 5-bit immediate.
> * config/riscv/predicates.md: Implement predicate
>   const_int5s_operand - signed 5 bit immediate.
> * doc/sourcebuild.texi: Add XCVbi documentation.
>
> gcc/testsuite/ChangeLog:
> * gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
> * gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
> * gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
> * gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
> * lib/target-supports.exp: Add proc for XCVbi.
> ---
>  gcc/common/config/riscv/riscv-common.cc   |  2 +
>  gcc/config/riscv/constraints.md   |  6 +++
>  gcc/config/riscv/corev.md | 14 ++
>  gcc/config/riscv/predicates.md|  4 ++
>  gcc/config/riscv/riscv.md | 11 -
>  gcc/config/riscv/riscv.opt|  2 +
>  gcc/doc/sourcebuild.texi  |  3 ++
>  .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++
>  .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++
>  .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++
>  .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++
>  gcc/testsuite/lib/target-supports.exp | 13 +
>  12 files changed, 184 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index 6a1978bd0e4..04631e007f0 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -313,6 +313,7 @@ static const struct riscv_ext_version 
> riscv_ext_version_table[] =
>{"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
>{"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
>{"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0},
>
>{"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
>{"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -1669,6 +1670,7 @@ static const riscv_ext_flag_table_t 
> riscv_ext_flag_table[] =
>{"xcvmac",_options::x_riscv_xcv_subext, MASK_XCVMAC},
>{"xcvalu",_options::x_riscv_xcv_subext, MASK_XCVALU},
>{"xcvelw",_options::x_riscv_xcv_subext, MASK_XCVELW},
> +  {"xcvbi", _options::x_riscv_xcv_subext, MASK_XCVBI},
>
>{"xtheadba",  _options::x_riscv_xthead_subext, MASK_XTHEADBA},
>{"xtheadbb",  _options::x_riscv_xthead_subext, MASK_XTHEADBB},
> diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
> index 2711efe68c5..718b4bd77df 100644
> --- a/gcc/config/riscv/constraints.md
> +++ b/gcc/config/riscv/constraints.md
> @@ -247,3 +247,9 @@
>(and (match_code "const_int")
> (and (match_test "IN_RANGE (ival, 0, 1073741823)")
>  (match_test "exact_log2 (ival + 1) != -1"
> +
> +(define_constraint "CV_bi_sign5"
> +  "@internal
> +   A 5-bit signed immediate for CORE-V Immediate Branch."
> +  (and (match_code "const_int")
> +   (match_test "IN_RANGE (ival, -16, 15)")))
> diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
> index 92bf0b5d6a6..f6a1f916d7e 100644
> --- a/gcc/config/riscv/corev.md
> +++ b/gcc/config/riscv/corev.md
> @@ -706,3 +706,17 @@
>
>[(set_attr "type" "load")
>(set_attr "mode" "SI")])
> +
> +;; XCVBI Builtins
> +(define_insn "cv_branch"
> +  [(set (pc)
> +   (if_then_else
> +(match_operator 1 "equality_operator"
> +[(match_operand:X 2 "register_operand" "r")
> + (match_operand:X 3 "const_int5s_operand" 
> "CV_bi_sign5")])
> +(label_ref (match_operand 0 "" ""))
> +   

[PATCH v2 3/3] RISC-V: Add support for XCVbi extension in CV32E40P

[Mary Bennett]

Spec: 
github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-builtin-spec.md

Contributors:
  Mary Bennett 
  Nandni Jamnadas 
  Pietra Ferreira 
  Charlie Keaney
  Jessica Mills
  Craig Blackmore 
  Simon Cook 
  Jeremy Bennett 
  Helene Chelin 

gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Create XCVbi extension
  support.
* config/riscv/riscv.opt: Likewise.
* config/riscv/corev.md: Implement cv_branch pattern
  for cv.beqimm and cv.bneimm.
* config/riscv/riscv.md: Change pattern priority so corev.md
  patterns run before riscv.md patterns.
* config/riscv/constraints.md: Implement constraints
  cv_bi_s5 - signed 5-bit immediate.
* config/riscv/predicates.md: Implement predicate
  const_int5s_operand - signed 5 bit immediate.
* doc/sourcebuild.texi: Add XCVbi documentation.

gcc/testsuite/ChangeLog:
* gcc.target/riscv/cv-bi-beqimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-beqimm-compile-2.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-1.c: New test.
* gcc.target/riscv/cv-bi-bneimm-compile-2.c: New test.
* lib/target-supports.exp: Add proc for XCVbi.
---
 gcc/common/config/riscv/riscv-common.cc   |  2 +
 gcc/config/riscv/constraints.md   |  6 +++
 gcc/config/riscv/corev.md | 14 ++
 gcc/config/riscv/predicates.md|  4 ++
 gcc/config/riscv/riscv.md | 11 -
 gcc/config/riscv/riscv.opt|  2 +
 gcc/doc/sourcebuild.texi  |  3 ++
 .../gcc.target/riscv/cv-bi-beqimm-compile-1.c | 17 +++
 .../gcc.target/riscv/cv-bi-beqimm-compile-2.c | 48 +++
 .../gcc.target/riscv/cv-bi-bneimm-compile-1.c | 17 +++
 .../gcc.target/riscv/cv-bi-bneimm-compile-2.c | 48 +++
 gcc/testsuite/lib/target-supports.exp | 13 +
 12 files changed, 184 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-beqimm-compile-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cv-bi-bneimm-compile-2.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 6a1978bd0e4..04631e007f0 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -313,6 +313,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xcvelw", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xcvbi", ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1669,6 +1670,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"xcvmac",_options::x_riscv_xcv_subext, MASK_XCVMAC},
   {"xcvalu",_options::x_riscv_xcv_subext, MASK_XCVALU},
   {"xcvelw",_options::x_riscv_xcv_subext, MASK_XCVELW},
+  {"xcvbi", _options::x_riscv_xcv_subext, MASK_XCVBI},
 
   {"xtheadba",  _options::x_riscv_xthead_subext, MASK_XTHEADBA},
   {"xtheadbb",  _options::x_riscv_xthead_subext, MASK_XTHEADBB},
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 2711efe68c5..718b4bd77df 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -247,3 +247,9 @@
   (and (match_code "const_int")
(and (match_test "IN_RANGE (ival, 0, 1073741823)")
 (match_test "exact_log2 (ival + 1) != -1"
+
+(define_constraint "CV_bi_sign5"
+  "@internal
+   A 5-bit signed immediate for CORE-V Immediate Branch."
+  (and (match_code "const_int")
+   (match_test "IN_RANGE (ival, -16, 15)")))
diff --git a/gcc/config/riscv/corev.md b/gcc/config/riscv/corev.md
index 92bf0b5d6a6..f6a1f916d7e 100644
--- a/gcc/config/riscv/corev.md
+++ b/gcc/config/riscv/corev.md
@@ -706,3 +706,17 @@
 
   [(set_attr "type" "load")
   (set_attr "mode" "SI")])
+
+;; XCVBI Builtins
+(define_insn "cv_branch"
+  [(set (pc)
+   (if_then_else
+(match_operator 1 "equality_operator"
+[(match_operand:X 2 "register_operand" "r")
+ (match_operand:X 3 "const_int5s_operand" 
"CV_bi_sign5")])
+(label_ref (match_operand 0 "" ""))
+(pc)))]
+  "TARGET_XCVBI"
+  "cv.b%C1imm\t%2,%3,%0"
+  [(set_attr "type" "branch")
+   (set_attr "mode" "none")])
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index a37d035fa61..69a6319c2c8 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -400,6 +400,10 @@
   (ior (match_operand 0 "register_operand")
(match_code "const_int")))
 
+(define_predicate "const_int5s_operand"
+  (and (match_code "const_int")
+