Re: [PATCH v3] RISC-V: Add autovec FP binary operations.
Hi Robin, Yes, you're right, this should not be necessary. This is more of a test for the execution environment than the compiler. I think Juzhe removed it already in his patch that enables the vector test suite. In the future we would use the checks that Joern added, not sure if they are already upstream All right, let's wait for further action. Thanks. -- Best, Lehua
Re: [PATCH v3] RISC-V: Add autovec FP binary operations.
Hi Lehua, > May I ask if the compiler options "-march=rv64gcv_zvfh -mabi=lp64d" > should be removed? Because we don't specify -march and -mabi when we > run testcase (so but why we need to specify the -march and -mabi in > this target check?), we run it with the default values. Assuming that > the default is rv64gcv_zvfh_zfh, `riscv_vector` check will fail > because compile and link with -march=rv64gcv will throw the following > error if I doesn't compile a multilibs compilers. But in fact > rv64gcv_zvfh_zfh contains rv64gcv, we should not let this case report > link error.: Yes, you're right, this should not be necessary. This is more of a test for the execution environment than the compiler. I think Juzhe removed it already in his patch that enables the vector test suite. In the future we would use the checks that Joern added, not sure if they are already upstream. Regards Robin
Re: [PATCH v3] RISC-V: Add autovec FP binary operations.
Hi Robin,
+# Return 1 if the we can build a vector example with proper -march flags
+# and the current target can execute it, 0 otherwise. Cache the result.
+
+proc check_effective_target_riscv_vector_hw { } {
+
+return [check_runtime riscv_vector_hw32 {
+int main (void)
+{
+asm ("vsetivli zero,8,e16,m1,ta,ma");
+asm ("vadd.vv v8,v8,v16" : : : "v8");
+return 0;
+}
+} "-march=rv32gcv -mabi=ilp32d"] || [check_runtime riscv_vector_hw64 {
+int main (void)
+{
+asm ("vsetivli zero,8,e16,m1,ta,ma");
+asm ("vadd.vv v8,v8,v16" : : : "v8");
+return 0;
+}
+} "-march=rv64gcv -mabi=lp64d"]
+}
+
+# Return 1 if the we can build a Zvfh vector example with proper -march flags
+# and the current target can execute it, 0 otherwise. Cache the result.
+
+proc check_effective_target_riscv_zvfh_hw { } {
+if ![check_effective_target_riscv_vector_hw] then {
+return 0
+}
+
+return [check_runtime riscv_zvfh_hw32 {
+int main (void)
+{
+asm ("vsetivli zero,8,e16,m1,ta,ma");
+asm ("vfadd.vv v8,v8,v16" : : : "v8");
+return 0;
+}
+} "-march=rv32gcv_zvfh -mabi=ilp32d"]
+|| [check_runtime riscv_zvfh_hw64 {
+int main (void)
+{
+asm ("vsetivli zero,8,e16,m1,ta,ma");
+asm ("vfadd.vv v8,v8,v16" : : : "v8");
+return 0;
+}
+} "-march=rv64gcv_zvfh -mabi=lp64d"]
May I ask if the compiler options "-march=rv64gcv_zvfh -mabi=lp64d"
should be removed? Because we don't specify -march and -mabi when we run
testcase (so but why we need to specify the -march and -mabi in this
target check?), we run it with the default values. Assuming that the
default is rv64gcv_zvfh_zfh, `riscv_vector` check will fail because
compile and link with -march=rv64gcv will throw the following error if I
doesn't compile a multilibs compilers. But in fact rv64gcv_zvfh_zfh
contains rv64gcv, we should not let this case report link error.:
riscv64-unknown-elf-gcc: fatal error: Cannot find suitable multilib set
for
'-march=rv64imafdcv_zicsr_zifencei_zve32f_zve32x_zve64d_zve64f_zve64x_zvl128b_zvl32b_zvl64b'/'-mabi=lp64d'
I think we should use the default march and mabi to check whether we can
compile and execute specified instructions.
--
Best,
Lehua
Re: [PATCH v3] RISC-V: Add autovec FP binary operations.
On 6/16/23 07:43, juzhe.zhong wrote: lgtm ACK for the trunk. jeff
[PATCH v3] RISC-V: Add autovec FP binary operations.
Hi, changes in v3: - No longer "dependent" on testsuite changes. Just the zvfh run testcases use riscv_zvfh_hw, i.e. require that we can compile, link the code as well as execute the resulting binary. - Renamed rounding modes (floating_point_rounding_mode feels a bit long-winded but well...) Regards Robin This implements the floating-point autovec expanders for binary operations: vfadd, vfsub, vfdiv, vfmul, vfmax, vfmin and adds tests. The existing tests are split up into non-_Float16 and _Float16 flavors as we cannot rely on the zvfh extension being present. As long as we do not have full middle-end support we need -ffast-math for the tests. In order to allow proper _Float16 support we need to disable promotion to float. This patch handles that similarly to TARGET_ZFH and TARGET_ZINX. This is not strictly accurate as the zvfh extension only requires the zfhmin i.e. just conversion to float and no actual operations. gcc/ChangeLog: * config/riscv/autovec.md (3): Implement binop expander. * config/riscv/riscv-protos.h (emit_vlmax_fp_insn): Declare. (emit_vlmax_fp_minmax_insn): Declare. (enum frm_field_enum): Rename this... (enum rounding_mode): ...to this. * config/riscv/riscv-v.cc (emit_vlmax_fp_insn): New function (emit_vlmax_fp_minmax_insn): New function. * config/riscv/riscv.cc (riscv_const_insns): Clarify const vector handling. (riscv_libgcc_floating_mode_supported_p): Adjust comment. (riscv_excess_precision): Do not convert to float for ZVFH. * config/riscv/vector-iterators.md: Add VF_AUTO iterator. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Add FP. * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c: Add FP. * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c: Add FP. * gcc.target/riscv/rvv/autovec/binop/vadd-template.h: Add FP. * gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Add FP. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Add FP. * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Add FP. * gcc.target/riscv/rvv/autovec/binop/vdiv-template.h: Add FP. * gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Add FP. * gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c: Add FP. * gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c: Add FP. * gcc.target/riscv/rvv/autovec/binop/vmax-template.h: Add FP. * gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Add FP. * gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c: Add FP. * gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c: Add FP. * gcc.target/riscv/rvv/autovec/binop/vmin-template.h: Add FP. * gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Add FP. * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Add FP. * gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Add FP. * gcc.target/riscv/rvv/autovec/binop/vmul-template.h: Add FP. * gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Add FP. * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Add FP. * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Add FP. * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Add FP. * gcc.target/riscv/rvv/autovec/binop/vsub-template.h: Add FP. * gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c: New test. * gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c: New test. * gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c: New test. * gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c: New test. * gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c: New test. * gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c: New test. * lib/target-supports.exp: Add riscv_vector_hw and riscv_zvfh_hw target selectors. --- gcc/config/riscv/autovec.md | 36 + gcc/config/riscv/riscv-protos.h | 8 +- gcc/config/riscv/riscv-v.cc | 74 ++- gcc/config/riscv/riscv.cc | 27 +-- gcc/config/riscv/vector-iterators.md | 28 +++ .../riscv/rvv/autovec/binop/vadd-run.c| 12 ++- .../riscv/rvv/autovec/binop/vadd-rv32gcv.c| 3 +- .../riscv/rvv/autovec/binop/vadd-rv64gcv.c| 3 +- .../riscv/rvv/autovec/binop/vadd-template.h | 11 ++- .../riscv/rvv/autovec/binop/vadd-zvfh-run.c | 54 ++ .../riscv/rvv/autovec/binop/vdiv-run.c| 8 +- .../riscv/rvv/autovec/binop/vdiv-rv32gcv.c| 7 +- .../riscv/rvv/autovec/binop/vdiv-rv64gcv.c| 7 +- .../riscv/rvv/autovec/binop/vdiv-template.h | 8 +- .../riscv/rvv/autovec/binop/vdiv-zvfh-run.c | 37 ++ .../riscv/rvv/autovec/binop/vmax-run.c| 9 ++- .../riscv/rvv/autovec/binop/vmax-rv32gcv.c| 3 +- .../riscv/rvv/autovec/binop/vmax-rv64gcv.c| 3 +-
