Re: [PATCH v4] LoongArch: Add support for TLS descriptors
On Wed, 2024-03-13 at 10:24 +0800, Xi Ruoyao wrote: > return TARGET_EXPLICIT_RELOCS > - ? "pcalau12i\t$r4,%%desc_pc_hi20(%1)\n\ > - \taddi.d\t%2,$r0,%%desc_pc_lo12(%1)\n\ > - \tlu32i.d\t%2,%%desc64_pc_lo20(%1)\n\ > - \tlu52i.d\t%2,%2,%%desc64_pc_hi12(%1)\n\ > - \tadd.d\t$r4,$r4,%2\n\ > - \tld.d\t$r1,$r4,%%desc_ld(%1)\n\ > - \tjirl\t$r1,$r1,%%desc_call(%1)" > - : "la.tls.desc\t%0,%2,%1"; > + ? "pcalau12i\t$r4,%%desc_pc_hi20(%0)\n\t" > + "addi.d\t%1,$r0,%%desc_pc_lo12(%0)\n\t" > + "lu32i.d\t%1,%%desc64_pc_lo20(%0)\n\t" > + "lu52i.d\t%1,%2,%%desc64_pc_hi12(%0)\n\t" Oops, the "%2" in the above line should be "%1". > + "add.d\t$r4,$r4,%1\n\t" > + "ld.d\t$r1,$r4,%%desc_ld(%0)\n\t" > + "jirl\t$r1,$r1,%%desc_call(%0)" > + : "la.tls.desc\t$r4,%1,%0"; -- Xi Ruoyao School of Aerospace Science and Technology, Xidian University
Re: [PATCH v4] LoongArch: Add support for TLS descriptors
On Wed, 2024-03-13 at 11:06 +0800, mengqinggang wrote:
>
> 在 2024/3/13 上午6:15, Xi Ruoyao 写道:
> > On Tue, 2024-03-12 at 17:20 +0800, mengqinggang wrote:
> > > +(define_insn "@got_load_tls_desc"
> > > + [(set (match_operand:P 0 "register_operand" "=r")
> > > + (unspec:P
> > > + [(match_operand:P 1 "symbolic_operand" "")]
> > > + UNSPEC_TLS_DESC))
> > > + (clobber (reg:SI FCC0_REGNUM))
> > > + (clobber (reg:SI FCC1_REGNUM))
> > > + (clobber (reg:SI FCC2_REGNUM))
> > > + (clobber (reg:SI FCC3_REGNUM))
> > > + (clobber (reg:SI FCC4_REGNUM))
> > > + (clobber (reg:SI FCC5_REGNUM))
> > > + (clobber (reg:SI FCC6_REGNUM))
> > > + (clobber (reg:SI FCC7_REGNUM))
> > > + (clobber (reg:SI RETURN_ADDR_REGNUM))]
> > > + "TARGET_TLS_DESC"
> > > +{
> > > + return TARGET_EXPLICIT_RELOCS
> > > + ? "pcalau12i\t$r4,%%desc_pc_hi20(%1)\n\
> > > + \taddi.d\t$r4,$r4,%%desc_pc_lo12(%1)\n\
> > > + \tld.d\t$r1,$r4,%%desc_ld(%1)\n\
> > > + \tjirl\t$r1,$r1,%%desc_call(%1)"
> > Use something like
> >
> > ? "pcalau12i\t$r4,%%desc_pc_hi20(%1)\n\t"
> > "addi.d\t$r4,$r4,%%desc_pc_lo12(%1)\n\t"
> > "ld.d\t$r1,$r4,%%desc_ld(%1)\n\t"
> > "jirl\t$r1,$r1,%%desc_call(%1)"
> > : "la.tls.desc\t%0,%1";
> >
> > to prevent additional white spaces in the output asm before tabs.
> >
> > > + : "la.tls.desc\t%0,%1";
> > > +}
> > > + [(set_attr "got" "load")
> > > + (set_attr "mode" "")
> > > + (set_attr "length" "16")])
> > > +
> > > +(define_insn "got_load_tls_desc_off64"
> > > + [(set (match_operand:DI 0 "register_operand" "=r")
> > > + (unspec:DI
> > > + [(match_operand:DI 1 "symbolic_operand" "")]
> > > + UNSPEC_TLS_DESC_OFF64))
> > > + (clobber (reg:SI FCC0_REGNUM))
> > > + (clobber (reg:SI FCC1_REGNUM))
> > > + (clobber (reg:SI FCC2_REGNUM))
> > > + (clobber (reg:SI FCC3_REGNUM))
> > > + (clobber (reg:SI FCC4_REGNUM))
> > > + (clobber (reg:SI FCC5_REGNUM))
> > > + (clobber (reg:SI FCC6_REGNUM))
> > > + (clobber (reg:SI FCC7_REGNUM))
> > > + (clobber (reg:SI RETURN_ADDR_REGNUM))
> > > + (clobber (match_operand:DI 2 "register_operand" "="))]
> > > + "TARGET_TLS_DESC && TARGET_CMODEL_EXTREME"
> > > +{
> > > + return TARGET_EXPLICIT_RELOCS
> > > + ? "pcalau12i\t$r4,%%desc_pc_hi20(%1)\n\
> > > + \taddi.d\t%2,$r0,%%desc_pc_lo12(%1)\n\
> > > + \tlu32i.d\t%2,%%desc64_pc_lo20(%1)\n\
> > > + \tlu52i.d\t%2,%2,%%desc64_pc_hi12(%1)\n\
> > > + \tadd.d\t$r4,$r4,%2\n\
> > > + \tld.d\t$r1,$r4,%%desc_ld(%1)\n\
> > > + \tjirl\t$r1,$r1,%%desc_call(%1)"
> > > + : "la.tls.desc\t%0,%2,%1";
> > Likewise.
> >
> > > +}
> > > + [(set_attr "got" "load")
> > > + (set_attr "length" "28")])
> > Otherwise OK.
> >
> > It's better to allow splitting these two instructions but we can do it
> > in another patch. And IMO it's better to enable TLS desc by default if
> > supported by both the assembler and the libc, but we'll have to defer it
> > until Glibc 2.40 release.
>
>
> Do we need to wait until LLVM also supports TLS DESC before setting it
> as default?
Hmm, maybe... I remember when we added R_LARCH_ALIGN lld was being
broken for a while.
--
Xi Ruoyao
School of Aerospace Science and Technology, Xidian University
Re: [PATCH v4] LoongArch: Add support for TLS descriptors
在 2024/3/13 上午6:15, Xi Ruoyao 写道:
On Tue, 2024-03-12 at 17:20 +0800, mengqinggang wrote:
+(define_insn "@got_load_tls_desc"
+ [(set (match_operand:P 0 "register_operand" "=r")
+ (unspec:P
+ [(match_operand:P 1 "symbolic_operand" "")]
+ UNSPEC_TLS_DESC))
+ (clobber (reg:SI FCC0_REGNUM))
+ (clobber (reg:SI FCC1_REGNUM))
+ (clobber (reg:SI FCC2_REGNUM))
+ (clobber (reg:SI FCC3_REGNUM))
+ (clobber (reg:SI FCC4_REGNUM))
+ (clobber (reg:SI FCC5_REGNUM))
+ (clobber (reg:SI FCC6_REGNUM))
+ (clobber (reg:SI FCC7_REGNUM))
+ (clobber (reg:SI RETURN_ADDR_REGNUM))]
+ "TARGET_TLS_DESC"
+{
+ return TARGET_EXPLICIT_RELOCS
+ ? "pcalau12i\t$r4,%%desc_pc_hi20(%1)\n\
+ \taddi.d\t$r4,$r4,%%desc_pc_lo12(%1)\n\
+ \tld.d\t$r1,$r4,%%desc_ld(%1)\n\
+ \tjirl\t$r1,$r1,%%desc_call(%1)"
Use something like
? "pcalau12i\t$r4,%%desc_pc_hi20(%1)\n\t"
"addi.d\t$r4,$r4,%%desc_pc_lo12(%1)\n\t"
"ld.d\t$r1,$r4,%%desc_ld(%1)\n\t"
"jirl\t$r1,$r1,%%desc_call(%1)"
: "la.tls.desc\t%0,%1";
to prevent additional white spaces in the output asm before tabs.
+ : "la.tls.desc\t%0,%1";
+}
+ [(set_attr "got" "load")
+ (set_attr "mode" "")
+ (set_attr "length" "16")])
+
+(define_insn "got_load_tls_desc_off64"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI
+ [(match_operand:DI 1 "symbolic_operand" "")]
+ UNSPEC_TLS_DESC_OFF64))
+ (clobber (reg:SI FCC0_REGNUM))
+ (clobber (reg:SI FCC1_REGNUM))
+ (clobber (reg:SI FCC2_REGNUM))
+ (clobber (reg:SI FCC3_REGNUM))
+ (clobber (reg:SI FCC4_REGNUM))
+ (clobber (reg:SI FCC5_REGNUM))
+ (clobber (reg:SI FCC6_REGNUM))
+ (clobber (reg:SI FCC7_REGNUM))
+ (clobber (reg:SI RETURN_ADDR_REGNUM))
+ (clobber (match_operand:DI 2 "register_operand" "="))]
+ "TARGET_TLS_DESC && TARGET_CMODEL_EXTREME"
+{
+ return TARGET_EXPLICIT_RELOCS
+ ? "pcalau12i\t$r4,%%desc_pc_hi20(%1)\n\
+ \taddi.d\t%2,$r0,%%desc_pc_lo12(%1)\n\
+ \tlu32i.d\t%2,%%desc64_pc_lo20(%1)\n\
+ \tlu52i.d\t%2,%2,%%desc64_pc_hi12(%1)\n\
+ \tadd.d\t$r4,$r4,%2\n\
+ \tld.d\t$r1,$r4,%%desc_ld(%1)\n\
+ \tjirl\t$r1,$r1,%%desc_call(%1)"
+ : "la.tls.desc\t%0,%2,%1";
Likewise.
+}
+ [(set_attr "got" "load")
+ (set_attr "length" "28")])
Otherwise OK.
It's better to allow splitting these two instructions but we can do it
in another patch. And IMO it's better to enable TLS desc by default if
supported by both the assembler and the libc, but we'll have to defer it
until Glibc 2.40 release.
Do we need to wait until LLVM also supports TLS DESC before setting it
as default?
Re: [PATCH v4] LoongArch: Add support for TLS descriptors
On Wed, 2024-03-13 at 06:56 +0800, Xi Ruoyao wrote:
> On Wed, 2024-03-13 at 06:15 +0800, Xi Ruoyao wrote:
> > > +(define_insn "@got_load_tls_desc"
> > > + [(set (match_operand:P 0 "register_operand" "=r")
>
> Hmm, and it looks like we should use (reg:P 4) instead of match_operand
> here, because the instruction does not work for a different register:
> with TARGET_EXPLICIT_RELOCS we are hard coding r4, and without
> TARGET_EXPLICIT_RELOCS the TLS desc function still only puts the return
> value in r4.
Suggested changes:
diff --git a/gcc/config/loongarch/loongarch.cc
b/gcc/config/loongarch/loongarch.cc
index 303666bf6d5..8f4d3f36c26 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -2954,10 +2954,10 @@ loongarch_legitimize_tls_address (rtx loc)
tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM);
if (TARGET_CMODEL_EXTREME)
- emit_insn (gen_got_load_tls_desc_off64 (a0, loc,
+ emit_insn (gen_got_load_tls_desc_off64 (loc,
gen_reg_rtx (DImode)));
else
- emit_insn (gen_got_load_tls_desc (Pmode, a0, loc));
+ emit_insn (gen_got_load_tls_desc (Pmode, loc));
emit_insn (gen_add3_insn (dest, a0, tp));
}
diff --git a/gcc/config/loongarch/loongarch.md
b/gcc/config/loongarch/loongarch.md
index 0a1a6a24f61..8e8f1012344 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -2772,9 +2772,9 @@ (define_insn "store_word"
;; Thread-Local Storage
(define_insn "@got_load_tls_desc"
- [(set (match_operand:P 0 "register_operand" "=r")
+ [(set (reg:P 4)
(unspec:P
- [(match_operand:P 1 "symbolic_operand" "")]
+ [(match_operand:P 0 "symbolic_operand" "")]
UNSPEC_TLS_DESC))
(clobber (reg:SI FCC0_REGNUM))
(clobber (reg:SI FCC1_REGNUM))
@@ -2788,20 +2788,20 @@ (define_insn "@got_load_tls_desc"
"TARGET_TLS_DESC"
{
return TARGET_EXPLICIT_RELOCS
-? "pcalau12i\t$r4,%%desc_pc_hi20(%1)\n\
- \taddi.d\t$r4,$r4,%%desc_pc_lo12(%1)\n\
- \tld.d\t$r1,$r4,%%desc_ld(%1)\n\
- \tjirl\t$r1,$r1,%%desc_call(%1)"
-: "la.tls.desc\t%0,%1";
+? "pcalau12i\t$r4,%%desc_pc_hi20(%0)\n\t"
+ "addi.d\t$r4,$r4,%%desc_pc_lo12(%0)\n\t"
+ "ld.d\t$r1,$r4,%%desc_ld(%0)\n\t"
+ "jirl\t$r1,$r1,%%desc_call(%0)"
+: "la.tls.desc\t$r4,%0";
}
[(set_attr "got" "load")
(set_attr "mode" "")
(set_attr "length" "16")])
(define_insn "got_load_tls_desc_off64"
- [(set (match_operand:DI 0 "register_operand" "=r")
+ [(set (reg:DI 4)
(unspec:DI
- [(match_operand:DI 1 "symbolic_operand" "")]
+ [(match_operand:DI 0 "symbolic_operand" "")]
UNSPEC_TLS_DESC_OFF64))
(clobber (reg:SI FCC0_REGNUM))
(clobber (reg:SI FCC1_REGNUM))
@@ -2812,18 +2812,18 @@ (define_insn "got_load_tls_desc_off64"
(clobber (reg:SI FCC6_REGNUM))
(clobber (reg:SI FCC7_REGNUM))
(clobber (reg:SI RETURN_ADDR_REGNUM))
-(clobber (match_operand:DI 2 "register_operand" "="))]
+(clobber (match_operand:DI 1 "register_operand" "="))]
"TARGET_TLS_DESC && TARGET_CMODEL_EXTREME"
{
return TARGET_EXPLICIT_RELOCS
-? "pcalau12i\t$r4,%%desc_pc_hi20(%1)\n\
- \taddi.d\t%2,$r0,%%desc_pc_lo12(%1)\n\
- \tlu32i.d\t%2,%%desc64_pc_lo20(%1)\n\
- \tlu52i.d\t%2,%2,%%desc64_pc_hi12(%1)\n\
- \tadd.d\t$r4,$r4,%2\n\
- \tld.d\t$r1,$r4,%%desc_ld(%1)\n\
- \tjirl\t$r1,$r1,%%desc_call(%1)"
-: "la.tls.desc\t%0,%2,%1";
+? "pcalau12i\t$r4,%%desc_pc_hi20(%0)\n\t"
+ "addi.d\t%1,$r0,%%desc_pc_lo12(%0)\n\t"
+ "lu32i.d\t%1,%%desc64_pc_lo20(%0)\n\t"
+ "lu52i.d\t%1,%2,%%desc64_pc_hi12(%0)\n\t"
+ "add.d\t$r4,$r4,%1\n\t"
+ "ld.d\t$r1,$r4,%%desc_ld(%0)\n\t"
+ "jirl\t$r1,$r1,%%desc_call(%0)"
+: "la.tls.desc\t$r4,%1,%0";
}
[(set_attr "got" "load")
(set_attr "length" "28")])
--
Xi Ruoyao
School of Aerospace Science and Technology, Xidian University
Re: [PATCH v4] LoongArch: Add support for TLS descriptors
On Wed, 2024-03-13 at 06:15 +0800, Xi Ruoyao wrote:
> > +(define_insn "@got_load_tls_desc"
> > + [(set (match_operand:P 0 "register_operand" "=r")
Hmm, and it looks like we should use (reg:P 4) instead of match_operand
here, because the instruction does not work for a different register:
with TARGET_EXPLICIT_RELOCS we are hard coding r4, and without
TARGET_EXPLICIT_RELOCS the TLS desc function still only puts the return
value in r4.
> > + (unspec:P
> > + [(match_operand:P 1 "symbolic_operand" "")]
> > + UNSPEC_TLS_DESC))
> > + (clobber (reg:SI FCC0_REGNUM))
> > + (clobber (reg:SI FCC1_REGNUM))
> > + (clobber (reg:SI FCC2_REGNUM))
> > + (clobber (reg:SI FCC3_REGNUM))
> > + (clobber (reg:SI FCC4_REGNUM))
> > + (clobber (reg:SI FCC5_REGNUM))
> > + (clobber (reg:SI FCC6_REGNUM))
> > + (clobber (reg:SI FCC7_REGNUM))
> > + (clobber (reg:SI RETURN_ADDR_REGNUM))]
> > + "TARGET_TLS_DESC"
> > +{
> > + return TARGET_EXPLICIT_RELOCS
> > + ? "pcalau12i\t$r4,%%desc_pc_hi20(%1)\n\
> > + \taddi.d\t$r4,$r4,%%desc_pc_lo12(%1)\n\
> > + \tld.d\t$r1,$r4,%%desc_ld(%1)\n\
> > + \tjirl\t$r1,$r1,%%desc_call(%1)"
>
> Use something like
>
> ? "pcalau12i\t$r4,%%desc_pc_hi20(%1)\n\t"
> "addi.d\t$r4,$r4,%%desc_pc_lo12(%1)\n\t"
> "ld.d\t$r1,$r4,%%desc_ld(%1)\n\t"
> "jirl\t$r1,$r1,%%desc_call(%1)"
> : "la.tls.desc\t%0,%1";
>
> to prevent additional white spaces in the output asm before tabs.
--
Xi Ruoyao
School of Aerospace Science and Technology, Xidian University
Re: [PATCH v4] LoongArch: Add support for TLS descriptors
On Tue, 2024-03-12 at 17:20 +0800, mengqinggang wrote:
> +(define_insn "@got_load_tls_desc"
> + [(set (match_operand:P 0 "register_operand" "=r")
> + (unspec:P
> + [(match_operand:P 1 "symbolic_operand" "")]
> + UNSPEC_TLS_DESC))
> + (clobber (reg:SI FCC0_REGNUM))
> + (clobber (reg:SI FCC1_REGNUM))
> + (clobber (reg:SI FCC2_REGNUM))
> + (clobber (reg:SI FCC3_REGNUM))
> + (clobber (reg:SI FCC4_REGNUM))
> + (clobber (reg:SI FCC5_REGNUM))
> + (clobber (reg:SI FCC6_REGNUM))
> + (clobber (reg:SI FCC7_REGNUM))
> + (clobber (reg:SI RETURN_ADDR_REGNUM))]
> + "TARGET_TLS_DESC"
> +{
> + return TARGET_EXPLICIT_RELOCS
> + ? "pcalau12i\t$r4,%%desc_pc_hi20(%1)\n\
> + \taddi.d\t$r4,$r4,%%desc_pc_lo12(%1)\n\
> + \tld.d\t$r1,$r4,%%desc_ld(%1)\n\
> + \tjirl\t$r1,$r1,%%desc_call(%1)"
Use something like
? "pcalau12i\t$r4,%%desc_pc_hi20(%1)\n\t"
"addi.d\t$r4,$r4,%%desc_pc_lo12(%1)\n\t"
"ld.d\t$r1,$r4,%%desc_ld(%1)\n\t"
"jirl\t$r1,$r1,%%desc_call(%1)"
: "la.tls.desc\t%0,%1";
to prevent additional white spaces in the output asm before tabs.
> + : "la.tls.desc\t%0,%1";
> +}
> + [(set_attr "got" "load")
> + (set_attr "mode" "")
> + (set_attr "length" "16")])
> +
> +(define_insn "got_load_tls_desc_off64"
> + [(set (match_operand:DI 0 "register_operand" "=r")
> + (unspec:DI
> + [(match_operand:DI 1 "symbolic_operand" "")]
> + UNSPEC_TLS_DESC_OFF64))
> + (clobber (reg:SI FCC0_REGNUM))
> + (clobber (reg:SI FCC1_REGNUM))
> + (clobber (reg:SI FCC2_REGNUM))
> + (clobber (reg:SI FCC3_REGNUM))
> + (clobber (reg:SI FCC4_REGNUM))
> + (clobber (reg:SI FCC5_REGNUM))
> + (clobber (reg:SI FCC6_REGNUM))
> + (clobber (reg:SI FCC7_REGNUM))
> + (clobber (reg:SI RETURN_ADDR_REGNUM))
> + (clobber (match_operand:DI 2 "register_operand" "="))]
> + "TARGET_TLS_DESC && TARGET_CMODEL_EXTREME"
> +{
> + return TARGET_EXPLICIT_RELOCS
> + ? "pcalau12i\t$r4,%%desc_pc_hi20(%1)\n\
> + \taddi.d\t%2,$r0,%%desc_pc_lo12(%1)\n\
> + \tlu32i.d\t%2,%%desc64_pc_lo20(%1)\n\
> + \tlu52i.d\t%2,%2,%%desc64_pc_hi12(%1)\n\
> + \tadd.d\t$r4,$r4,%2\n\
> + \tld.d\t$r1,$r4,%%desc_ld(%1)\n\
> + \tjirl\t$r1,$r1,%%desc_call(%1)"
> + : "la.tls.desc\t%0,%2,%1";
Likewise.
> +}
> + [(set_attr "got" "load")
> + (set_attr "length" "28")])
Otherwise OK.
It's better to allow splitting these two instructions but we can do it
in another patch. And IMO it's better to enable TLS desc by default if
supported by both the assembler and the libc, but we'll have to defer it
until Glibc 2.40 release.
--
Xi Ruoyao
School of Aerospace Science and Technology, Xidian University
[PATCH v4] LoongArch: Add support for TLS descriptors
Add support for TLS descriptors on normal code model and extreme code model.
Normal code model instruction sequence:
-mno-explicit-relocs:
la.tls.desc $r4, s
add.d $r12, $r4, $r2
-mexplicit-relocs:
pcalau12i $r4,%desc_pc_hi20(s)
addi.d $r4,$r4,%desc_pc_lo12(s)
ld.d$r1,$r4,%desc_ld(s)
jirl$r1,$r1,%desc_call(s)
add.d $r12, $r4, $r2
Extreme code model instruction sequence:
-mno-explicit-relocs:
la.tls.desc $r4, $r12, s
add.d $r12, $r4, $r2
-mexplicit-relocs:
pcalau12i $r4,%desc_pc_hi20(s)
addi.d $r12,$r0,%desc_pc_lo12(s)
lu32i.d $r12,%desc64_pc_lo20(s)
lu52i.d $r12,$r12,%desc64_pc_hi12(s)
add.d $r4,$r4,$r12
ld.d$r1,$r4,%desc_ld(s)
jirl$r1,$r1,%desc_call(s)
add.d $r12, $r4, $r2
The default is still traditional TLS model, but can be configured with
--with-tls={trad,desc}. The default can change to TLS descriptors once
libc and LLVM support this.
gcc/ChangeLog:
* config.gcc: Add --with-tls option to change TLS flavor.
* config/loongarch/genopts/loongarch.opt.in: Add -mtls-dialect to
configure TLS flavor.
* config/loongarch/loongarch-def.h (struct loongarch_target): Add
tls_dialect.
* config/loongarch/loongarch-driver.cc (la_driver_init): Add tls
flavor.
* config/loongarch/loongarch-opts.cc (loongarch_init_target): Add
tls_dialect.
(loongarch_config_target): Ditto.
(loongarch_update_gcc_opt_status): Ditto.
* config/loongarch/loongarch-opts.h (loongarch_init_target):Ditto.
(TARGET_TLS_DESC): New define.
* config/loongarch/loongarch.cc (loongarch_symbol_insns): Add TLS DESC
instructions sequence length.
(loongarch_legitimize_tls_address): New TLS DESC instruction sequence.
(loongarch_option_override_internal): Add la_opt_tls_dialect.
(loongarch_option_restore): Add la_target.tls_dialect.
* config/loongarch/loongarch.md (@got_load_tls_desc): Normal
code model for TLS DESC.
(got_load_tls_desc_off64): Extreme code model for TLS DESC.
* config/loongarch/loongarch.opt: Regenerated.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/cmodel-extreme-1.c: Add -mtls-dialect=trad.
* gcc.target/loongarch/cmodel-extreme-2.c: Ditto.
* gcc.target/loongarch/explicit-relocs-auto-tls-ld-gd.c: Ditto.
* gcc.target/loongarch/explicit-relocs-medium-call36-auto-tls-ld-gd.c:
Ditto.
* gcc.target/loongarch/func-call-medium-1.c: Ditto.
* gcc.target/loongarch/func-call-medium-2.c: Ditto.
* gcc.target/loongarch/func-call-medium-3.c: Ditto.
* gcc.target/loongarch/func-call-medium-4.c: Ditto.
* gcc.target/loongarch/tls-extreme-macro.c: Ditto.
* gcc.target/loongarch/tls-gd-noplt.c: Ditto.
* gcc.target/loongarch/explicit-relocs-auto-extreme-tls-desc.c: New
test.
* gcc.target/loongarch/explicit-relocs-auto-tls-desc.c: New test.
* gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c: New test.
* gcc.target/loongarch/explicit-relocs-tls-desc.c: New test.
---
Changes v3 -> v4:
- Add TLS descriptors test cases.
Changes v2 -> v3:
- Set default to traditional TLS model.
- Add support for -mexplicit-relocs and extreme code model.
Changes v1 -> v2:
- Clobber fcc0-fcc7 registers in got_load_tls_desc template.
- Support --with-tls in configure.
v3 link: https://sourceware.org/pipermail/gcc-patches/2024-March/647578.html
v2 link: https://sourceware.org/pipermail/gcc-patches/2024-February/646817.html
v1 link: https://sourceware.org/pipermail/gcc-patches/2023-December/638907.html
gcc/config.gcc| 19 +-
gcc/config/loongarch/genopts/loongarch.opt.in | 14
gcc/config/loongarch/loongarch-def.h | 7 ++
gcc/config/loongarch/loongarch-driver.cc | 2 +-
gcc/config/loongarch/loongarch-opts.cc| 12 +++-
gcc/config/loongarch/loongarch-opts.h | 2 +
gcc/config/loongarch/loongarch.cc | 48 +
gcc/config/loongarch/loongarch.md | 68 +++
gcc/config/loongarch/loongarch.opt| 14
.../gcc.target/loongarch/cmodel-extreme-1.c | 2 +-
.../gcc.target/loongarch/cmodel-extreme-2.c | 2 +-
.../explicit-relocs-auto-extreme-tls-desc.c | 10 +++
.../loongarch/explicit-relocs-auto-tls-desc.c | 10 +++
.../explicit-relocs-auto-tls-ld-gd.c | 2 +-
.../explicit-relocs-extreme-tls-desc.c| 16 +
...icit-relocs-medium-call36-auto-tls-ld-gd.c | 2 +-
.../loongarch/explicit-relocs-tls-desc.c | 13
.../gcc.target/loongarch/func-call-medium-1.c | 2 +-
.../gcc.target/loongarch/func-call-medium-2.c | 2 +-
.../gcc.target/loongarch/func-call-medium-3.c | 2 +-
.../gcc.target/loongarch/func-call-medium-4.c | 2 +-
.../gcc.target/loongarch/tls-extreme-macro.c
