Re: [PATCH v4 4/6, Committed] [MIPS] Add Loongson 3A1000 processor support

[Paul Hua]

Hi Gerald,

patch send to here: https://gcc.gnu.org/ml/gcc-patches/2018-12/msg01785.html

thanks.



On Fri, Dec 28, 2018 at 12:50 AM Gerald Pfeifer  wrote:
>
> Hi Paul and Matthew,
>
> I believe it would be good to get this and other MIPS changes covered
> in the GCC 9 release notes at https://gcc.gnu.org/gcc-9/changes.html .
>
> Gerald
>
> PS: https://gcc.gnu.org/about.html has background how to go about this.

Re: [PATCH v4 4/6, Committed] [MIPS] Add Loongson 3A1000 processor support

[Gerald Pfeifer]

Hi Paul and Matthew,

I believe it would be good to get this and other MIPS changes covered
in the GCC 9 release notes at https://gcc.gnu.org/gcc-9/changes.html .

Gerald

PS: https://gcc.gnu.org/about.html has background how to go about this.

[PATCH v4 4/6, Committed] [MIPS] Add Loongson 3A1000 processor support

[Paul Hua]

On Tue, Oct 16, 2018 at 10:50 AM Paul Hua  wrote:
>
>
From ef10d77f03e693299611e6b4eee2ae6375a5841d Mon Sep 17 00:00:00 2001
From: Chenghua Xu 
Date: Tue, 6 Nov 2018 21:12:46 +0800
Subject: [PATCH 4/6] Add support for Loongson 3A1000 processor.

gcc/
	* config/mips/loongson3a.md: Rename to ...
	* config/mips/gs464.md: ... here.
	* config/mips/mips-cpus.def: Define gs464; Add loongson3a
	as an alias of gs464 processor.
	* config/mips/mips-tables.opt: Regenerate.
	* config/mips/mips.c (mips_issue_rate): Use PROCESSOR_GS464
	instead of PROCESSOR_LOONGSON_3A.
	(mips_multipass_dfa_lookahead): Use TUNE_GS464 instead of
	TUNE_LOONGSON_3A.
	(mips_option_override): Enable MMI and EXT for gs464.
	* config/mips/mips.h: Rename TARGET_LOONGSON_3A to TARGET_GS464;
	Rename TUNE_LOONGSON_3A to TUNE_GS464.
	(MIPS_ISA_LEVEL_SPEC): Infer mips64r2 from gs464.
	(ISA_HAS_ODD_SPREG, ISA_AVOID_DIV_HILO, ISA_HAS_FUSED_MADD4,
	ISA_HAS_UNFUSED_MADD4): Use TARGET_GS464 instead of
	TARGET_LOONGSON_3A.
	* config/mips/mips.md: Include gs464.md instead of loongson3a.md.
	(processor): Add gs464;
	* doc/invoke.texi: Add gs464 to supported architectures.
---
 gcc/config/mips/gs464.md| 137 
 gcc/config/mips/loongson3a.md   | 137 
 gcc/config/mips/mips-cpus.def   |   3 +-
 gcc/config/mips/mips-tables.opt |  19 +++--
 gcc/config/mips/mips.c  |   6 +-
 gcc/config/mips/mips.h  |  17 ++--
 gcc/config/mips/mips.md |   4 +-
 gcc/doc/invoke.texi |   2 +-
 8 files changed, 165 insertions(+), 160 deletions(-)
 create mode 100644 gcc/config/mips/gs464.md
 delete mode 100644 gcc/config/mips/loongson3a.md

diff --git a/gcc/config/mips/gs464.md b/gcc/config/mips/gs464.md
new file mode 100644
index 000..82efb66786f
--- /dev/null
+++ b/gcc/config/mips/gs464.md
@@ -0,0 +1,137 @@
+;; Pipeline model for Loongson gs464 cores.
+
+;; Copyright (C) 2011-2018 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 3, or (at your
+;; option) any later version.
+;;
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; .
+
+;; Uncomment the following line to output automata for debugging.
+;; (automata_option "v")
+
+;; Automaton for integer instructions.
+(define_automaton "gs464_a_alu")
+
+;; Automaton for floating-point instructions.
+(define_automaton "gs464_a_falu")
+
+;; Automaton for memory operations.
+(define_automaton "gs464_a_mem")
+
+;; Describe the resources.
+
+(define_cpu_unit "gs464_alu1" "gs464_a_alu")
+(define_cpu_unit "gs464_alu2" "gs464_a_alu")
+(define_cpu_unit "gs464_mem" "gs464_a_mem")
+(define_cpu_unit "gs464_falu1" "gs464_a_falu")
+(define_cpu_unit "gs464_falu2" "gs464_a_falu")
+
+;; Describe instruction reservations.
+
+(define_insn_reservation "gs464_arith" 1
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "arith,clz,const,logical,
+			move,nop,shift,signext,slt"))
+  "gs464_alu1 | gs464_alu2")
+
+(define_insn_reservation "gs464_branch" 1
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "branch,jump,call,condmove,trap"))
+  "gs464_alu1")
+
+(define_insn_reservation "gs464_mfhilo" 1
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "mfhi,mflo,mthi,mtlo"))
+  "gs464_alu2")
+
+;; Operation imul3nc is fully pipelined.
+(define_insn_reservation "gs464_imul3nc" 5
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "imul3nc"))
+  "gs464_alu2")
+
+(define_insn_reservation "gs464_imul" 7
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "imul,imadd"))
+  "gs464_alu2 * 7")
+
+(define_insn_reservation "gs464_idiv_si" 12
+  (and (eq_attr "cpu" "gs464")
+   (and (eq_attr "type" "idiv")
+	(eq_attr "mode" "SI")))
+  "gs464_alu2 * 12")
+
+(define_insn_reservation "gs464_idiv_di" 25
+  (and (eq_attr "cpu" "gs464")
+   (and (eq_attr "type" "idiv")
+	(eq_attr "mode" "DI")))
+  "gs464_alu2 * 25")
+
+(define_insn_reservation "gs464_load" 3
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "load"))
+  "gs464_mem")
+
+(define_insn_reservation "gs464_fpload" 4
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "load,mfc,mtc"))
+  "gs464_mem")
+
+(define_insn_reservation "gs464_prefetch" 0
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "prefetch,prefetchx"))
+  "gs464_mem")
+
+(define_insn_reservation "gs464_store" 0
+  (and (eq_attr "cpu" "gs464")
+   (eq_attr "type" "store,fpstore,fpidxstore"))
+  "gs464_mem")
+
+;; All the fp operations can