Re: [PATCH ver 2] rs6000, __builtin_set_fpscr_rn add retrun value
on 2023/7/11 03:18, Carl Love wrote: > On Fri, 2023-07-07 at 12:06 +0800, Kewen.Lin wrote: >> Hi Carl, >> >> Some more minor comments are inline below on top of Peter's >> insightful >> review comments. >> >> on 2023/7/1 08:58, Carl Love wrote: >>> GCC maintainers: >>> >>> Ver 2, Went back thru the requirements and emails. Not sure where >>> I >>> came up with the requirement for an overloaded version with double >>> argument. Removed the overloaded version with the double >>> argument. >>> Added the macro to announce if the __builtin_set_fpscr_rn returns a >>> void or a double with the FPSCR bits. Updated the documentation >>> file. >>> Retested on Power 8 BE/LE, Power 9 BE/LE, Power 10 LE. Redid the >>> test >>> file. Per request, the original test file functionality was not >>> changed. Just changed the name from test_fpscr_rn_builtin.c to >>> test_fpscr_rn_builtin_1.c. Put new tests for the return values >>> into a >>> new test file, test_fpscr_rn_builtin_2.c. >>> >>> The GLibC team requested a builtin to replace the mffscrn and >>> mffscrniinline asm instructions in the GLibC code. Previously >>> there >>> was discussion on adding builtins for the mffscrn instructions. >>> >>> https://gcc.gnu.org/pipermail/gcc-patches/2023-May/620261.html >>> >>> In the end, it was felt that it would be to extend the existing >>> __builtin_set_fpscr_rn builtin to return a double instead of a void >>> type. The desire is that we could have the functionality of the >>> mffscrn and mffscrni instructions on older ISAs. The two >>> instructions >>> were initially added in ISA 3.0. The __builtin_set_fpscr_rn has >>> the >>> needed functionality to set the RN field using the mffscrn and >>> mffscrni >>> instructions if ISA 3.0 is supported or fall back to using logical >>> instructions to mask and set the bits for earlier ISAs. The >>> instructions return the current value of the FPSCR fields DRN, VE, >>> OE, >>> UE, ZE, XE, NI, RN bit positions then update the RN bit positions >>> with >>> the new RN value provided. >>> >>> The current __builtin_set_fpscr_rn builtin has a return type of >>> void. >>> So, changing the return type to double and returning the FPSCR >>> fields >>> DRN, VE, OE, UE, ZE, XE, NI, RN bit positions would then give the >>> functionally equivalent of the mffscrn and mffscrni >>> instructions. Any >>> current uses of the builtin would just ignore the return value yet >>> any >>> new uses could use the return value. So the requirement is for the >>> change to the __builtin_set_fpscr_rn builtin to be backwardly >>> compatible and work for all ISAs. >>> >>> The following patch changes the return type of the >>> __builtin_set_fpscr_rn builtin from void to double. The return >>> value >>> is the current value of the various FPSCR fields DRN, VE, OE, UE, >>> ZE, >>> XE, NI, RN bit positions when the builtin is called. The builtin >>> then >>> updated the RN field with the new value provided as an argument to >>> the >>> builtin. The patch adds new testcases to test_fpscr_rn_builtin.c >>> to >>> check that the builtin returns the current value of the FPSCR >>> fields >>> and then updates the RN field. >>> >>> The GLibC team has reviewed the patch to make sure it met their >>> needs >>> as a drop in replacement for the inline asm mffscr and mffscrni >>> statements in the GLibC code. T >>> >>> The patch has been tested on Power 8 LE/BE, Power 9 LE/BE and Power >>> 10 >>> LE. >>> >>> Please let me know if the patch is acceptable for >>> mainline. Thanks. >>> >>>Carl >>> >>> >>> -- >>> rs6000, __builtin_set_fpscr_rn add retrun value >>> >>> Change the return value from void to double. The return value >>> consists of >>> the FPSCR fields DRN, VE, OE, UE, ZE, XE, NI, RN bit >>> positions. Add an >>> overloaded version which accepts a double argument. >>> >>> The test powerpc/test_fpscr_rn_builtin.c is updated to add tests >>> for the >>> double reterun value and the new double argument. >>> >>> gcc/ChangeLog: >>> * config/rs6000/rs6000-builtins.def (__builtin_set_fpscr_rn): >>> Update >>> builtin definition return type. >>> * config/rs6000-c.cc(rs6000_target_modify_macros): Add check, >>> define >>> __SET_FPSCR_RN_RETURNS_FPSCR__ macro. >>> * config/rs6000/rs6000.md ((rs6000_get_fpscr_fields): New >>> define_expand. >>> (rs6000_update_fpscr_rn_field): New define_expand. >>> (rs6000_set_fpscr_rn): Addedreturn argument. Updated >>> to use new >>> rs6000_get_fpscr_fields and rs6000_update_fpscr_rn_field define >>> _expands. >>> * doc/extend.texi (__builtin_set_fpscr_rn): Update description >>> for >>> the return value and new double argument. Add descripton for >>> __SET_FPSCR_RN_RETURNS_FPSCR__ macro. >>> >>> gcc/testsuite/ChangeLog: >>> gcc.target/powerpc/test_fpscr_rn_builtin.c: Renamed to >>> test_fpscr_rn_builtin_1.c. Added comment. >>>
Re: [PATCH ver 2] rs6000, __builtin_set_fpscr_rn add retrun value
On Fri, 2023-07-07 at 12:06 +0800, Kewen.Lin wrote: > Hi Carl, > > Some more minor comments are inline below on top of Peter's > insightful > review comments. > > on 2023/7/1 08:58, Carl Love wrote: > > GCC maintainers: > > > > Ver 2, Went back thru the requirements and emails. Not sure where > > I > > came up with the requirement for an overloaded version with double > > argument. Removed the overloaded version with the double > > argument. > > Added the macro to announce if the __builtin_set_fpscr_rn returns a > > void or a double with the FPSCR bits. Updated the documentation > > file. > > Retested on Power 8 BE/LE, Power 9 BE/LE, Power 10 LE. Redid the > > test > > file. Per request, the original test file functionality was not > > changed. Just changed the name from test_fpscr_rn_builtin.c to > > test_fpscr_rn_builtin_1.c. Put new tests for the return values > > into a > > new test file, test_fpscr_rn_builtin_2.c. > > > > The GLibC team requested a builtin to replace the mffscrn and > > mffscrniinline asm instructions in the GLibC code. Previously > > there > > was discussion on adding builtins for the mffscrn instructions. > > > > https://gcc.gnu.org/pipermail/gcc-patches/2023-May/620261.html > > > > In the end, it was felt that it would be to extend the existing > > __builtin_set_fpscr_rn builtin to return a double instead of a void > > type. The desire is that we could have the functionality of the > > mffscrn and mffscrni instructions on older ISAs. The two > > instructions > > were initially added in ISA 3.0. The __builtin_set_fpscr_rn has > > the > > needed functionality to set the RN field using the mffscrn and > > mffscrni > > instructions if ISA 3.0 is supported or fall back to using logical > > instructions to mask and set the bits for earlier ISAs. The > > instructions return the current value of the FPSCR fields DRN, VE, > > OE, > > UE, ZE, XE, NI, RN bit positions then update the RN bit positions > > with > > the new RN value provided. > > > > The current __builtin_set_fpscr_rn builtin has a return type of > > void. > > So, changing the return type to double and returning the FPSCR > > fields > > DRN, VE, OE, UE, ZE, XE, NI, RN bit positions would then give the > > functionally equivalent of the mffscrn and mffscrni > > instructions. Any > > current uses of the builtin would just ignore the return value yet > > any > > new uses could use the return value. So the requirement is for the > > change to the __builtin_set_fpscr_rn builtin to be backwardly > > compatible and work for all ISAs. > > > > The following patch changes the return type of the > > __builtin_set_fpscr_rn builtin from void to double. The return > > value > > is the current value of the various FPSCR fields DRN, VE, OE, UE, > > ZE, > > XE, NI, RN bit positions when the builtin is called. The builtin > > then > > updated the RN field with the new value provided as an argument to > > the > > builtin. The patch adds new testcases to test_fpscr_rn_builtin.c > > to > > check that the builtin returns the current value of the FPSCR > > fields > > and then updates the RN field. > > > > The GLibC team has reviewed the patch to make sure it met their > > needs > > as a drop in replacement for the inline asm mffscr and mffscrni > > statements in the GLibC code. T > > > > The patch has been tested on Power 8 LE/BE, Power 9 LE/BE and Power > > 10 > > LE. > > > > Please let me know if the patch is acceptable for > > mainline. Thanks. > > > >Carl > > > > > > -- > > rs6000, __builtin_set_fpscr_rn add retrun value > > > > Change the return value from void to double. The return value > > consists of > > the FPSCR fields DRN, VE, OE, UE, ZE, XE, NI, RN bit > > positions. Add an > > overloaded version which accepts a double argument. > > > > The test powerpc/test_fpscr_rn_builtin.c is updated to add tests > > for the > > double reterun value and the new double argument. > > > > gcc/ChangeLog: > > * config/rs6000/rs6000-builtins.def (__builtin_set_fpscr_rn): > > Update > > builtin definition return type. > > * config/rs6000-c.cc(rs6000_target_modify_macros): Add check, > > define > > __SET_FPSCR_RN_RETURNS_FPSCR__ macro. > > * config/rs6000/rs6000.md ((rs6000_get_fpscr_fields): New > > define_expand. > > (rs6000_update_fpscr_rn_field): New define_expand. > > (rs6000_set_fpscr_rn): Addedreturn argument. Updated > > to use new > > rs6000_get_fpscr_fields and rs6000_update_fpscr_rn_field define > > _expands. > > * doc/extend.texi (__builtin_set_fpscr_rn): Update description > > for > > the return value and new double argument. Add descripton for > > __SET_FPSCR_RN_RETURNS_FPSCR__ macro. > > > > gcc/testsuite/ChangeLog: > > gcc.target/powerpc/test_fpscr_rn_builtin.c: Renamed to > > test_fpscr_rn_builtin_1.c. Added comment. > >
Re: [PATCH ver 2] rs6000, __builtin_set_fpscr_rn add retrun value
On Thu, 2023-07-06 at 17:54 -0500, Peter Bergner wrote:
> On 6/30/23 7:58 PM, Carl Love via Gcc-patches wrote:
> > rs6000, __builtin_set_fpscr_rn add retrun value
>
> s/retrun/return/
>
> Maybe better written as:
>
> rs6000: Add return value to __builtin_set_fpscr_rn
Changed subject, fixed misspelling.
>
>
> > Change the return value from void to double. The return value
> > consists of
> > the FPSCR fields DRN, VE, OE, UE, ZE, XE, NI, RN bit
> > positions. Add an
> > overloaded version which accepts a double argument.
>
> You're not adding an overloaded version anymore, so I think you can
> just
> remove the last sentence.
Yup, didn't get that removed when removing the overloaded instance.
fixed.
>
>
>
> > The test powerpc/test_fpscr_rn_builtin.c is updated to add tests
> > for the
> > double reterun value and the new double argument.
>
> s/reterun/return/ ...and there is no double argument anymore, so
> that
> part can be removed.
Fixed. Note, the new return value tests were moved to new test file.
>
>
>
> > * config/rs6000/rs6000.md ((rs6000_get_fpscr_fields): New
> > define_expand.
>
> Too many '('.
fixed.
>
>
>
> > (rs6000_set_fpscr_rn): Addedreturn argument. Updated
> > to use new
>
> Looks like a after Added instead of a space.
>
>
> > rs6000_get_fpscr_fields and rs6000_update_fpscr_rn_field define
> > _expands.
>
> Don't split define_expand across two lines.
Fixed.
>
>
>
> > * doc/extend.texi (__builtin_set_fpscr_rn): Update description
> > for
> > the return value and new double argument. Add descripton for
> > __SET_FPSCR_RN_RETURNS_FPSCR__ macro.
>
> s/descripton/description/
Fixed.
>
>
>
>
>
>
> > + /* Tell the user the __builtin_set_fpscr_rn now returns the
> > FPSCR fields
> > + in a double. Originally the builtin returned void. */
>
> Either:
> 1) s/Tell the user the __builtin_set_fpscr_rn/Tell the user
> __builtin_set_fpscr_rn/
> 2) s/the __builtin_set_fpscr_rn now/the __builtin_set_fpscr_rn
> built-in now/
>
>
> > + if ((flags & OPTION_MASK_SOFT_FLOAT) == 0)
> > + rs6000_define_or_undefine_macro (define_p,
> > "__SET_FPSCR_RN_RETURNS_FPSCR__");
>
> This doesn't look like it's indented correctly.
>
>
Fixed indentation.
>
>
> > +(define_expand "rs6000_get_fpscr_fields"
> > + [(match_operand:DF 0 "gpc_reg_operand")]
> > + "TARGET_HARD_FLOAT"
> > +{
> > + /* Extract fields bits 29:31 (DRN) and bits 56:63 (VE, OE, UE,
> > ZE, XE, NI,
> > + RN) from the FPSCR and return them. */
> > + rtx tmp_df = gen_reg_rtx (DFmode);
> > + rtx tmp_di = gen_reg_rtx (DImode);
> > +
> > + emit_insn (gen_rs6000_mffs (tmp_df));
> > + tmp_di = simplify_gen_subreg (DImode, tmp_df, DFmode, 0);
> > + emit_insn (gen_anddi3 (tmp_di, tmp_di, GEN_INT
> > (0x000700FFULL)));
> > + rtx tmp_rtn = simplify_gen_subreg (DFmode, tmp_di, DImode, 0);
> > + emit_move_insn (operands[0], tmp_rtn);
> > + DONE;
> > +})
>
> This doesn't look correct. You first set tmp_di to a new reg rtx but
> then
> throw that away with the return value of simplify_gen_subreg(). I'm
> guessing
> you want that tmp_di as a gen_reg_rtx for the destination of the
> gen_anddi3, so
> you probably want a different rtx for the subreg that feeds the
> gen_anddi3.
OK, fixed the use of the tmp values. Note the define_expand was
inlined into define_expand "rs6000_set_fpscr_rn per comments from
Kewen. Inlining allows the reuse some of the tmp values.
>
>
>
> > +(define_expand "rs6000_update_fpscr_rn_field"
> > + [(match_operand:DI 0 "gpc_reg_operand")]
> > + "TARGET_HARD_FLOAT"
> > +{
> > + /* Insert the new RN value from operands[0] into FPSCR bit
> > [62:63]. */
> > + rtx tmp_di = gen_reg_rtx (DImode);
> > + rtx tmp_df = gen_reg_rtx (DFmode);
> > +
> > + emit_insn (gen_rs6000_mffs (tmp_df));
> > + tmp_di = simplify_gen_subreg (DImode, tmp_df, DFmode, 0);
>
> Ditto.
Fixed.
>
>
>
>
> > +The @code{__builtin_set_fpscr_rn} builtin allows changing both of
> > the floating
> > +point rounding mode bits and returning the various FPSCR fields
> > before the RN
> > +field is updated. The builtin returns a double consisting of the
> > initial value
> > +of the FPSCR fields DRN, VE, OE, UE, ZE, XE, NI, and RN bit
> > positions with all
> > +other bits set to zero. The builtin argument is a 2-bit value for
> > the new RN
> > +field value. The argument can either be an @code{const int} or
> > stored in a
> > +variable. Earlier versions of @code{__builtin_set_fpscr_rn}
> > returned void. A
> > +@code{__SET_FPSCR_RN_RETURNS_FPSCR__} macro has been added. If
> > defined, then
> > +the @code{__builtin_set_fpscr_rn} builtin returns the FPSCR
> > fields. If not
> > +defined, the @code{__builtin_set_fpscr_rn} does not return a
> > vaule. If the
> > +@option{-msoft-float} option is used, the
> > @code{__builtin_set_fpscr_rn} builtin
> > +will not return a value.
>
> Multiple occurrences of "builtin" that should be spelled
Re: [PATCH ver 2] rs6000, __builtin_set_fpscr_rn add retrun value
On 7/7/23 12:08 AM, Kewen.Lin wrote:
> on 2023/7/7 07:00, Peter Bergner wrote:
>> On 7/6/23 5:54 PM, Peter Bergner wrote:
>>> On 6/30/23 7:58 PM, Carl Love via Gcc-patches wrote:
+++ b/gcc/testsuite/gcc.target/powerpc/test_fpscr_rn_builtin_2.c
@@ -0,0 +1,153 @@
+/* { dg-do run { target { powerpc*-*-* } } } */
>>>
>>> powerpc*-*-* is the default for this test directory, so you can drop that,
>>> but you need to disable this test for soft-float systems, so you probably
>>> want:
>>>
>>> /* { dg-do run { target powerpc_fprs } } */
>>
>> We actually want something like powerpc_fprs_hw, but that doesn't exist.
>>
>
> Yeah, good point! I noticed that we have a few test cases which need to
> check soft-float env as well but they don't, I didn't find any related
> issues have been reported, so I would assume that there are very few
> actual testings on this area. Based on this, I'm not sure if it's worthy
> to add a new effective target for it. Personally I'm happy with just using
> powerpc_fprs here to keep it simple. :)
I think powerpc_fprs_hw can be added later by someone if they care.
Using powerpc_fprs is an improvement over powerpc*-*-*, since it will
reduce some FAILs, just not all of them a powerpc_fprs_hw would.
I doubt many people are running the testsuite on real ppc hardware
that doesn't have an FP unit.
Peter
Re: [PATCH ver 2] rs6000, __builtin_set_fpscr_rn add retrun value
on 2023/7/7 07:00, Peter Bergner wrote:
> On 7/6/23 5:54 PM, Peter Bergner wrote:
>> On 6/30/23 7:58 PM, Carl Love via Gcc-patches wrote:
>>> +++ b/gcc/testsuite/gcc.target/powerpc/test_fpscr_rn_builtin_2.c
>>> @@ -0,0 +1,153 @@
>>> +/* { dg-do run { target { powerpc*-*-* } } } */
>>
>> powerpc*-*-* is the default for this test directory, so you can drop that,
>> but you need to disable this test for soft-float systems, so you probably
>> want:
>>
>> /* { dg-do run { target powerpc_fprs } } */
>
> We actually want something like powerpc_fprs_hw, but that doesn't exist.
>
Yeah, good point! I noticed that we have a few test cases which need to
check soft-float env as well but they don't, I didn't find any related
issues have been reported, so I would assume that there are very few
actual testings on this area. Based on this, I'm not sure if it's worthy
to add a new effective target for it. Personally I'm happy with just using
powerpc_fprs here to keep it simple. :)
BR,
Kewen
Re: [PATCH ver 2] rs6000, __builtin_set_fpscr_rn add retrun value
Hi Carl, Some more minor comments are inline below on top of Peter's insightful review comments. on 2023/7/1 08:58, Carl Love wrote: > > GCC maintainers: > > Ver 2, Went back thru the requirements and emails. Not sure where I > came up with the requirement for an overloaded version with double > argument. Removed the overloaded version with the double argument. > Added the macro to announce if the __builtin_set_fpscr_rn returns a > void or a double with the FPSCR bits. Updated the documentation file. > Retested on Power 8 BE/LE, Power 9 BE/LE, Power 10 LE. Redid the test > file. Per request, the original test file functionality was not > changed. Just changed the name from test_fpscr_rn_builtin.c to > test_fpscr_rn_builtin_1.c. Put new tests for the return values into a > new test file, test_fpscr_rn_builtin_2.c. > > The GLibC team requested a builtin to replace the mffscrn and > mffscrniinline asm instructions in the GLibC code. Previously there > was discussion on adding builtins for the mffscrn instructions. > > https://gcc.gnu.org/pipermail/gcc-patches/2023-May/620261.html > > In the end, it was felt that it would be to extend the existing > __builtin_set_fpscr_rn builtin to return a double instead of a void > type. The desire is that we could have the functionality of the > mffscrn and mffscrni instructions on older ISAs. The two instructions > were initially added in ISA 3.0. The __builtin_set_fpscr_rn has the > needed functionality to set the RN field using the mffscrn and mffscrni > instructions if ISA 3.0 is supported or fall back to using logical > instructions to mask and set the bits for earlier ISAs. The > instructions return the current value of the FPSCR fields DRN, VE, OE, > UE, ZE, XE, NI, RN bit positions then update the RN bit positions with > the new RN value provided. > > The current __builtin_set_fpscr_rn builtin has a return type of void. > So, changing the return type to double and returning the FPSCR fields > DRN, VE, OE, UE, ZE, XE, NI, RN bit positions would then give the > functionally equivalent of the mffscrn and mffscrni instructions. Any > current uses of the builtin would just ignore the return value yet any > new uses could use the return value. So the requirement is for the > change to the __builtin_set_fpscr_rn builtin to be backwardly > compatible and work for all ISAs. > > The following patch changes the return type of the > __builtin_set_fpscr_rn builtin from void to double. The return value > is the current value of the various FPSCR fields DRN, VE, OE, UE, ZE, > XE, NI, RN bit positions when the builtin is called. The builtin then > updated the RN field with the new value provided as an argument to the > builtin. The patch adds new testcases to test_fpscr_rn_builtin.c to > check that the builtin returns the current value of the FPSCR fields > and then updates the RN field. > > The GLibC team has reviewed the patch to make sure it met their needs > as a drop in replacement for the inline asm mffscr and mffscrni > statements in the GLibC code. T > > The patch has been tested on Power 8 LE/BE, Power 9 LE/BE and Power 10 > LE. > > Please let me know if the patch is acceptable for mainline. Thanks. > >Carl > > > -- > rs6000, __builtin_set_fpscr_rn add retrun value > > Change the return value from void to double. The return value consists of > the FPSCR fields DRN, VE, OE, UE, ZE, XE, NI, RN bit positions. Add an > overloaded version which accepts a double argument. > > The test powerpc/test_fpscr_rn_builtin.c is updated to add tests for the > double reterun value and the new double argument. > > gcc/ChangeLog: > * config/rs6000/rs6000-builtins.def (__builtin_set_fpscr_rn): Update > builtin definition return type. > * config/rs6000-c.cc(rs6000_target_modify_macros): Add check, define > __SET_FPSCR_RN_RETURNS_FPSCR__ macro. > * config/rs6000/rs6000.md ((rs6000_get_fpscr_fields): New > define_expand. > (rs6000_update_fpscr_rn_field): New define_expand. > (rs6000_set_fpscr_rn): Addedreturn argument. Updated to use new > rs6000_get_fpscr_fields and rs6000_update_fpscr_rn_field define >_expands. > * doc/extend.texi (__builtin_set_fpscr_rn): Update description for > the return value and new double argument. Add descripton for > __SET_FPSCR_RN_RETURNS_FPSCR__ macro. > > gcc/testsuite/ChangeLog: > gcc.target/powerpc/test_fpscr_rn_builtin.c: Renamed to > test_fpscr_rn_builtin_1.c. Added comment. > gcc.target/powerpc/test_fpscr_rn_builtin_2.c: New test for the > return value of __builtin_set_fpscr_rn builtin. > --- > gcc/config/rs6000/rs6000-builtins.def | 2 +- > gcc/config/rs6000/rs6000-c.cc | 4 + > gcc/config/rs6000/rs6000.md | 87 +++--- > gcc/doc/extend.texi | 26 ++- >
Re: [PATCH ver 2] rs6000, __builtin_set_fpscr_rn add retrun value
On 7/6/23 5:54 PM, Peter Bergner wrote:
> On 6/30/23 7:58 PM, Carl Love via Gcc-patches wrote:
>> +++ b/gcc/testsuite/gcc.target/powerpc/test_fpscr_rn_builtin_2.c
>> @@ -0,0 +1,153 @@
>> +/* { dg-do run { target { powerpc*-*-* } } } */
>
> powerpc*-*-* is the default for this test directory, so you can drop that,
> but you need to disable this test for soft-float systems, so you probably
> want:
>
> /* { dg-do run { target powerpc_fprs } } */
We actually want something like powerpc_fprs_hw, but that doesn't exist.
Peter
Re: [PATCH ver 2] rs6000, __builtin_set_fpscr_rn add retrun value
On 6/30/23 7:58 PM, Carl Love via Gcc-patches wrote:
> rs6000, __builtin_set_fpscr_rn add retrun value
s/retrun/return/
Maybe better written as:
rs6000: Add return value to __builtin_set_fpscr_rn
> Change the return value from void to double. The return value consists of
> the FPSCR fields DRN, VE, OE, UE, ZE, XE, NI, RN bit positions. Add an
> overloaded version which accepts a double argument.
You're not adding an overloaded version anymore, so I think you can just
remove the last sentence.
> The test powerpc/test_fpscr_rn_builtin.c is updated to add tests for the
> double reterun value and the new double argument.
s/reterun/return/ ...and there is no double argument anymore, so that
part can be removed.
> * config/rs6000/rs6000.md ((rs6000_get_fpscr_fields): New
> define_expand.
Too many '('.
> (rs6000_set_fpscr_rn): Addedreturn argument. Updated to use new
Looks like a after Added instead of a space.
> rs6000_get_fpscr_fields and rs6000_update_fpscr_rn_field define
>_expands.
Don't split define_expand across two lines.
> * doc/extend.texi (__builtin_set_fpscr_rn): Update description for
> the return value and new double argument. Add descripton for
> __SET_FPSCR_RN_RETURNS_FPSCR__ macro.
s/descripton/description/
> + /* Tell the user the __builtin_set_fpscr_rn now returns the FPSCR fields
> + in a double. Originally the builtin returned void. */
Either:
1) s/Tell the user the __builtin_set_fpscr_rn/Tell the user
__builtin_set_fpscr_rn/
2) s/the __builtin_set_fpscr_rn now/the __builtin_set_fpscr_rn built-in now/
> + if ((flags & OPTION_MASK_SOFT_FLOAT) == 0)
> + rs6000_define_or_undefine_macro (define_p,
> "__SET_FPSCR_RN_RETURNS_FPSCR__");
This doesn't look like it's indented correctly.
> +(define_expand "rs6000_get_fpscr_fields"
> + [(match_operand:DF 0 "gpc_reg_operand")]
> + "TARGET_HARD_FLOAT"
> +{
> + /* Extract fields bits 29:31 (DRN) and bits 56:63 (VE, OE, UE, ZE, XE, NI,
> + RN) from the FPSCR and return them. */
> + rtx tmp_df = gen_reg_rtx (DFmode);
> + rtx tmp_di = gen_reg_rtx (DImode);
> +
> + emit_insn (gen_rs6000_mffs (tmp_df));
> + tmp_di = simplify_gen_subreg (DImode, tmp_df, DFmode, 0);
> + emit_insn (gen_anddi3 (tmp_di, tmp_di, GEN_INT (0x000700FFULL)));
> + rtx tmp_rtn = simplify_gen_subreg (DFmode, tmp_di, DImode, 0);
> + emit_move_insn (operands[0], tmp_rtn);
> + DONE;
> +})
This doesn't look correct. You first set tmp_di to a new reg rtx but then
throw that away with the return value of simplify_gen_subreg(). I'm guessing
you want that tmp_di as a gen_reg_rtx for the destination of the gen_anddi3, so
you probably want a different rtx for the subreg that feeds the gen_anddi3.
> +(define_expand "rs6000_update_fpscr_rn_field"
> + [(match_operand:DI 0 "gpc_reg_operand")]
> + "TARGET_HARD_FLOAT"
> +{
> + /* Insert the new RN value from operands[0] into FPSCR bit [62:63]. */
> + rtx tmp_di = gen_reg_rtx (DImode);
> + rtx tmp_df = gen_reg_rtx (DFmode);
> +
> + emit_insn (gen_rs6000_mffs (tmp_df));
> + tmp_di = simplify_gen_subreg (DImode, tmp_df, DFmode, 0);
Ditto.
> +The @code{__builtin_set_fpscr_rn} builtin allows changing both of the
> floating
> +point rounding mode bits and returning the various FPSCR fields before the RN
> +field is updated. The builtin returns a double consisting of the initial
> value
> +of the FPSCR fields DRN, VE, OE, UE, ZE, XE, NI, and RN bit positions with
> all
> +other bits set to zero. The builtin argument is a 2-bit value for the new RN
> +field value. The argument can either be an @code{const int} or stored in a
> +variable. Earlier versions of @code{__builtin_set_fpscr_rn} returned void.
> A
> +@code{__SET_FPSCR_RN_RETURNS_FPSCR__} macro has been added. If defined, then
> +the @code{__builtin_set_fpscr_rn} builtin returns the FPSCR fields. If not
> +defined, the @code{__builtin_set_fpscr_rn} does not return a vaule. If the
> +@option{-msoft-float} option is used, the @code{__builtin_set_fpscr_rn}
> builtin
> +will not return a value.
Multiple occurrences of "builtin" that should be spelled "built-in" (not in the
built-in function name itself though).
> +/* Originally the __builtin_set_fpscr_rn builtin was defined to return
> + void. It was later extended to return a double with the various
> + FPSCR bits. The extended builtin is inteded to be a drop in replacement
> + for the original version. This test is for the original version of the
> + builtin and should work exactly as before. */
Ditto.
> +++ b/gcc/testsuite/gcc.target/powerpc/test_fpscr_rn_builtin_2.c
> @@ -0,0 +1,153 @@
> +/* { dg-do run { target { powerpc*-*-* } } } */
powerpc*-*-* is the default for this test directory, so you can drop that,
but you need to disable this test for soft-float systems, so you probably want:
/* { dg-do run { target powerpc_fprs } } */
I know you didn't write it, but
[PATCH ver 2] rs6000, __builtin_set_fpscr_rn add retrun value
GCC maintainers:
Ver 2, Went back thru the requirements and emails. Not sure where I
came up with the requirement for an overloaded version with double
argument. Removed the overloaded version with the double argument.
Added the macro to announce if the __builtin_set_fpscr_rn returns a
void or a double with the FPSCR bits. Updated the documentation file.
Retested on Power 8 BE/LE, Power 9 BE/LE, Power 10 LE. Redid the test
file. Per request, the original test file functionality was not
changed. Just changed the name from test_fpscr_rn_builtin.c to
test_fpscr_rn_builtin_1.c. Put new tests for the return values into a
new test file, test_fpscr_rn_builtin_2.c.
The GLibC team requested a builtin to replace the mffscrn and
mffscrniinline asm instructions in the GLibC code. Previously there
was discussion on adding builtins for the mffscrn instructions.
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/620261.html
In the end, it was felt that it would be to extend the existing
__builtin_set_fpscr_rn builtin to return a double instead of a void
type. The desire is that we could have the functionality of the
mffscrn and mffscrni instructions on older ISAs. The two instructions
were initially added in ISA 3.0. The __builtin_set_fpscr_rn has the
needed functionality to set the RN field using the mffscrn and mffscrni
instructions if ISA 3.0 is supported or fall back to using logical
instructions to mask and set the bits for earlier ISAs. The
instructions return the current value of the FPSCR fields DRN, VE, OE,
UE, ZE, XE, NI, RN bit positions then update the RN bit positions with
the new RN value provided.
The current __builtin_set_fpscr_rn builtin has a return type of void.
So, changing the return type to double and returning the FPSCR fields
DRN, VE, OE, UE, ZE, XE, NI, RN bit positions would then give the
functionally equivalent of the mffscrn and mffscrni instructions. Any
current uses of the builtin would just ignore the return value yet any
new uses could use the return value. So the requirement is for the
change to the __builtin_set_fpscr_rn builtin to be backwardly
compatible and work for all ISAs.
The following patch changes the return type of the
__builtin_set_fpscr_rn builtin from void to double. The return value
is the current value of the various FPSCR fields DRN, VE, OE, UE, ZE,
XE, NI, RN bit positions when the builtin is called. The builtin then
updated the RN field with the new value provided as an argument to the
builtin. The patch adds new testcases to test_fpscr_rn_builtin.c to
check that the builtin returns the current value of the FPSCR fields
and then updates the RN field.
The GLibC team has reviewed the patch to make sure it met their needs
as a drop in replacement for the inline asm mffscr and mffscrni
statements in the GLibC code. T
The patch has been tested on Power 8 LE/BE, Power 9 LE/BE and Power 10
LE.
Please let me know if the patch is acceptable for mainline. Thanks.
Carl
--
rs6000, __builtin_set_fpscr_rn add retrun value
Change the return value from void to double. The return value consists of
the FPSCR fields DRN, VE, OE, UE, ZE, XE, NI, RN bit positions. Add an
overloaded version which accepts a double argument.
The test powerpc/test_fpscr_rn_builtin.c is updated to add tests for the
double reterun value and the new double argument.
gcc/ChangeLog:
* config/rs6000/rs6000-builtins.def (__builtin_set_fpscr_rn): Update
builtin definition return type.
* config/rs6000-c.cc(rs6000_target_modify_macros): Add check, define
__SET_FPSCR_RN_RETURNS_FPSCR__ macro.
* config/rs6000/rs6000.md ((rs6000_get_fpscr_fields): New
define_expand.
(rs6000_update_fpscr_rn_field): New define_expand.
(rs6000_set_fpscr_rn): Addedreturn argument. Updated to use new
rs6000_get_fpscr_fields and rs6000_update_fpscr_rn_field define
_expands.
* doc/extend.texi (__builtin_set_fpscr_rn): Update description for
the return value and new double argument. Add descripton for
__SET_FPSCR_RN_RETURNS_FPSCR__ macro.
gcc/testsuite/ChangeLog:
gcc.target/powerpc/test_fpscr_rn_builtin.c: Renamed to
test_fpscr_rn_builtin_1.c. Added comment.
gcc.target/powerpc/test_fpscr_rn_builtin_2.c: New test for the
return value of __builtin_set_fpscr_rn builtin.
---
gcc/config/rs6000/rs6000-builtins.def | 2 +-
gcc/config/rs6000/rs6000-c.cc | 4 +
gcc/config/rs6000/rs6000.md | 87 +++---
gcc/doc/extend.texi | 26 ++-
...rn_builtin.c => test_fpscr_rn_builtin_1.c} | 6 +
.../powerpc/test_fpscr_rn_builtin_2.c | 153 ++
6 files changed, 246 insertions(+), 32 deletions(-)
rename gcc/testsuite/gcc.target/powerpc/{test_fpscr_rn_builtin.c =>
test_fpscr_rn_builtin_1.c} (92%)
create mode 100644
