Re: [PING][PATCH v2] RISC-V: Split unordered FP comparisons into individual RTL insns

[Maciej W. Rozycki]

Hi Kito,

> I am convinced that is OK for now, I agree modeling fflags would be a
> rabbit hole, I tried to build a full GNU toolchain with my quick patch
> and saw many ICE during build libraries, that definitely should be a
> long-term optimization project.
> 
> Although I'm thinking if we should default -fno-trapping-math for
> RISC-V, because RISC-V didn't trap for any floating point operations,
> however I think that would be another topic.

 No need to do anything for RISC-V I believe, as Richard has mentioned 
that's been his plan for GCC 13 compiler-wide; see the discussion here:
 for 
further details.

> so you got my LGTM :)

 I have applied this change now then, thank you for your review.

  Maciej

Re: [PING][PATCH v2] RISC-V: Split unordered FP comparisons into individual RTL insns

[Kito Cheng via Gcc-patches]

Hi Maciej:

I am convinced that is OK for now, I agree modeling fflags would be a
rabbit hole, I tried to build a full GNU toolchain with my quick patch
and saw many ICE during build libraries, that definitely should be a
long-term optimization project.

Although I'm thinking if we should default -fno-trapping-math for
RISC-V, because RISC-V didn't trap for any floating point operations,
however I think that would be another topic.

so you got my LGTM :)




On Mon, Jul 18, 2022 at 11:43 PM Maciej W. Rozycki  wrote:
>
> On Mon, 4 Jul 2022, Maciej W. Rozycki wrote:
>
> > These instructions are only produced via an expander already, so change
> > the expander to emit individual RTL insns for each machine instruction
> > in the ultimate ultimate sequence produced rather than deferring to a
> > single RTL insn producing the whole sequence at once.
>
>  Ping for:
>
> 
>
>   Maciej

[PING][PATCH v2] RISC-V: Split unordered FP comparisons into individual RTL insns

[Maciej W. Rozycki]

On Mon, 4 Jul 2022, Maciej W. Rozycki wrote:

> These instructions are only produced via an expander already, so change 
> the expander to emit individual RTL insns for each machine instruction 
> in the ultimate ultimate sequence produced rather than deferring to a 
> single RTL insn producing the whole sequence at once.

 Ping for:



  Maciej