Re: [Patch, microblaze]: Add optimized lshrsi3
On 07/08/14 00:38, Nagaraju Mekala wrote:
Hi Michael,
-Original Message-
From: Michael Eager [mailto:ea...@eagerm.com]
Sent: Tuesday, July 01, 2014 11:12 AM
To: David Holsgrove; gcc-patches@gcc.gnu.org
Cc: Edgar Iglesias; John Williams; Vidhumouli Hunsigida; Nagaraju Mekala; Ajit
Kumar Agarwal
Subject: Re: [Patch, microblaze]: Add optimized lshrsi3
On 02/13/14 21:48, David Holsgrove wrote:
Hi Michael,
Sorry about the delay in reviewing this patch.
I see number of failures in the new lshrsi_Os_1.c test case:
PASS: gcc.target/microblaze/others/lshrsi_Os_1.c -O0 (test for excess errors)
PASS: gcc.target/microblaze/others/lshrsi_Os_1.c -O0 scan-assembler-not srli
FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O0 scan-assembler
ori\tr18,r0
FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O0 scan-assembler
addk\tr([0-9]|[1-2][0-9]|3[0-1]),r([0-9]|[1-2][0-9]|3[0-1]),r0
This testcase should only run with -Os and -mno-xl-barrel-shift flags.
Testcase and Patch description are commented accordingly.
/* { dg-options -Os -mno-xl-barrel-shift } */
Please let us know if you still face any issues after compiling with above
flags.
Send an updated patch which corrects this problem.
--
Michael Eagerea...@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
RE: [Patch, microblaze]: Add optimized lshrsi3
Hi Michael, -Original Message- From: Michael Eager [mailto:ea...@eagerm.com] Sent: Tuesday, July 01, 2014 11:12 AM To: David Holsgrove; gcc-patches@gcc.gnu.org Cc: Edgar Iglesias; John Williams; Vidhumouli Hunsigida; Nagaraju Mekala; Ajit Kumar Agarwal Subject: Re: [Patch, microblaze]: Add optimized lshrsi3 On 02/13/14 21:48, David Holsgrove wrote: Hi Michael, -Original Message- From: Michael Eager [mailto:ea...@eagerm.com] Sent: Sunday, 9 February 2014 2:58 am To: David Holsgrove; gcc-patches@gcc.gnu.org Cc: Edgar Iglesias; John Williams; Vidhumouli Hunsigida; Nagaraju Mekala Subject: Re: [Patch, microblaze]: Add optimized lshrsi3 On 11/25/13 23:53, David Holsgrove wrote: Add optimized lshrsi3 instruction, to be used when optimizing for size with immediate values over 5 Changelog 2013-11-26 Nagaraju Mekala nagaraju.mek...@xilinx.com * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn. David -- Please put the description of the patch in the text of the email, rather than hiding it within an attached patch. The patch describes a very specific situation where this patch will have an effect. Please provide a test case. Updated version of patch attached with testcase. New Changelog entries are; Changelog 2013-11-26 David Holsgrove david.holsgr...@xilinx.com * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn ChangeLog/testsuite 2014-02-12 David Holsgrove david.holsgr...@xilinx.com * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test. Sorry about the delay in reviewing this patch. I see number of failures in the new lshrsi_Os_1.c test case: PASS: gcc.target/microblaze/others/lshrsi_Os_1.c -O0 (test for excess errors) PASS: gcc.target/microblaze/others/lshrsi_Os_1.c -O0 scan-assembler-not srli FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O0 scan-assembler ori\tr18,r0 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O0 scan-assembler addk\tr([0-9]|[1-2][0-9]|3[0-1]),r([0-9]|[1-2][0-9]|3[0-1]),r0 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O0 scan-assembler addik\tr18,r18,-1 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O0 scan-assembler bneid\tr18,.-4 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O0 scan-assembler srl\tr([0-9]|[1-2][0-9]|3[0-1]),r([0-9]|[1-2][0-9]|3[0-1]) PASS: gcc.target/microblaze/others/lshrsi_Os_1.c -O1 (test for excess errors) PASS: gcc.target/microblaze/others/lshrsi_Os_1.c -O1 scan-assembler-not srli FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O1 scan-assembler ori\tr18,r0 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O1 scan-assembler addk\tr([0-9]|[1-2][0-9]|3[0-1]),r([0-9]|[1-2][0-9]|3[0-1]),r0 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O1 scan-assembler addik\tr18,r18,-1 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O1 scan-assembler bneid\tr18,.-4 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O1 scan-assembler srl\tr([0-9]|[1-2][0-9]|3[0-1]),r([0-9]|[1-2][0-9]|3[0-1]) PASS: gcc.target/microblaze/others/lshrsi_Os_1.c -O2 (test for excess errors) PASS: gcc.target/microblaze/others/lshrsi_Os_1.c -O2 scan-assembler-not srli FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O2 scan-assembler ori\tr18,r0 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O2 scan-assembler addk\tr([0-9]|[1-2][0-9]|3[0-1]),r([0-9]|[1-2][0-9]|3[0-1]),r0 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O2 scan-assembler addik\tr18,r18,-1 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O2 scan-assembler bneid\tr18,.-4 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O2 scan-assembler srl\tr([0-9]|[1-2][0-9]|3[0-1]),r([0-9]|[1-2][0-9]|3[0-1]) PASS: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -fomit-frame-pointer (test for excess errors) PASS: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -fomit-frame-pointer scan-assembler-not srli FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -fomit-frame-pointer scan-assembler ori\tr18,r0 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -fomit-frame-pointer scan-assembler addk\tr([0-9]|[1-2][0-9]|3[0-1]),r([0-9]|[1-2][0-9]|3[0-1]),r0 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -fomit-frame-pointer scan-assembler addik\tr18,r18,-1 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -fomit-frame-pointer scan-assembler bneid\tr18,.-4 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -fomit-frame-pointer scan-assembler srl\tr([0-9]|[1-2][0-9]|3[0-1]),r([0-9]|[1-2][0-9]|3[0-1]) PASS: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -g (test for excess errors) PASS: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -g scan-assembler-not srli FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -g scan-assembler ori\tr18,r0 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -g scan-assembler addk\tr([0-9]|[1-2][0-9]|3[0-1]),r([0-9]|[1-2][0-9]|3[0-1
Re: [Patch, microblaze]: Add optimized lshrsi3
On 02/13/14 21:48, David Holsgrove wrote: Hi Michael, -Original Message- From: Michael Eager [mailto:ea...@eagerm.com] Sent: Sunday, 9 February 2014 2:58 am To: David Holsgrove; gcc-patches@gcc.gnu.org Cc: Edgar Iglesias; John Williams; Vidhumouli Hunsigida; Nagaraju Mekala Subject: Re: [Patch, microblaze]: Add optimized lshrsi3 On 11/25/13 23:53, David Holsgrove wrote: Add optimized lshrsi3 instruction, to be used when optimizing for size with immediate values over 5 Changelog 2013-11-26 Nagaraju Mekala nagaraju.mek...@xilinx.com * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn. David -- Please put the description of the patch in the text of the email, rather than hiding it within an attached patch. The patch describes a very specific situation where this patch will have an effect. Please provide a test case. Updated version of patch attached with testcase. New Changelog entries are; Changelog 2013-11-26 David Holsgrove david.holsgr...@xilinx.com * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn ChangeLog/testsuite 2014-02-12 David Holsgrove david.holsgr...@xilinx.com * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test. Sorry about the delay in reviewing this patch. I see number of failures in the new lshrsi_Os_1.c test case: PASS: gcc.target/microblaze/others/lshrsi_Os_1.c -O0 (test for excess errors) PASS: gcc.target/microblaze/others/lshrsi_Os_1.c -O0 scan-assembler-not srli FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O0 scan-assembler ori\tr18,r0 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O0 scan-assembler addk\tr([0-9]|[1-2][0-9]|3[0-1]),r([0-9]|[1-2][0-9]|3[0-1]),r0 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O0 scan-assembler addik\tr18,r18,-1 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O0 scan-assembler bneid\tr18,.-4 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O0 scan-assembler srl\tr([0-9]|[1-2][0-9]|3[0-1]),r([0-9]|[1-2][0-9]|3[0-1]) PASS: gcc.target/microblaze/others/lshrsi_Os_1.c -O1 (test for excess errors) PASS: gcc.target/microblaze/others/lshrsi_Os_1.c -O1 scan-assembler-not srli FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O1 scan-assembler ori\tr18,r0 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O1 scan-assembler addk\tr([0-9]|[1-2][0-9]|3[0-1]),r([0-9]|[1-2][0-9]|3[0-1]),r0 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O1 scan-assembler addik\tr18,r18,-1 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O1 scan-assembler bneid\tr18,.-4 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O1 scan-assembler srl\tr([0-9]|[1-2][0-9]|3[0-1]),r([0-9]|[1-2][0-9]|3[0-1]) PASS: gcc.target/microblaze/others/lshrsi_Os_1.c -O2 (test for excess errors) PASS: gcc.target/microblaze/others/lshrsi_Os_1.c -O2 scan-assembler-not srli FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O2 scan-assembler ori\tr18,r0 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O2 scan-assembler addk\tr([0-9]|[1-2][0-9]|3[0-1]),r([0-9]|[1-2][0-9]|3[0-1]),r0 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O2 scan-assembler addik\tr18,r18,-1 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O2 scan-assembler bneid\tr18,.-4 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O2 scan-assembler srl\tr([0-9]|[1-2][0-9]|3[0-1]),r([0-9]|[1-2][0-9]|3[0-1]) PASS: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -fomit-frame-pointer (test for excess errors) PASS: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -fomit-frame-pointer scan-assembler-not srli FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -fomit-frame-pointer scan-assembler ori\tr18,r0 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -fomit-frame-pointer scan-assembler addk\tr([0-9]|[1-2][0-9]|3[0-1]),r([0-9]|[1-2][0-9]|3[0-1]),r0 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -fomit-frame-pointer scan-assembler addik\tr18,r18,-1 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -fomit-frame-pointer scan-assembler bneid\tr18,.-4 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -fomit-frame-pointer scan-assembler srl\tr([0-9]|[1-2][0-9]|3[0-1]),r([0-9]|[1-2][0-9]|3[0-1]) PASS: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -g (test for excess errors) PASS: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -g scan-assembler-not srli FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -g scan-assembler ori\tr18,r0 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -g scan-assembler addk\tr([0-9]|[1-2][0-9]|3[0-1]),r([0-9]|[1-2][0-9]|3[0-1]),r0 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -g scan-assembler addik\tr18,r18,-1 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -g scan-assembler bneid\tr18,.-4 FAIL: gcc.target/microblaze/others/lshrsi_Os_1.c -O3 -g scan-assembler srl\tr([0-9]|[1-2][0-9]|3[0-1]),r([0-9]|[1-2][0-9]|3[0-1]) PASS: gcc.target
Re: [Patch, microblaze]: Add optimized lshrsi3
On 02/13/14 21:48, David Holsgrove wrote: Hi Michael, -Original Message- From: Michael Eager [mailto:ea...@eagerm.com] Sent: Sunday, 9 February 2014 2:58 am To: David Holsgrove; gcc-patches@gcc.gnu.org Cc: Edgar Iglesias; John Williams; Vidhumouli Hunsigida; Nagaraju Mekala Subject: Re: [Patch, microblaze]: Add optimized lshrsi3 On 11/25/13 23:53, David Holsgrove wrote: Add optimized lshrsi3 instruction, to be used when optimizing for size with immediate values over 5 Changelog 2013-11-26 Nagaraju Mekala nagaraju.mek...@xilinx.com * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn. David -- Please put the description of the patch in the text of the email, rather than hiding it within an attached patch. The patch describes a very specific situation where this patch will have an effect. Please provide a test case. Updated version of patch attached with testcase. New Changelog entries are; Changelog 2013-11-26 David Holsgrove david.holsgr...@xilinx.com * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn ChangeLog/testsuite 2014-02-12 David Holsgrove david.holsgr...@xilinx.com * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test. thanks, David Thanks. -- Michael Eagerea...@eagercon.com 1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
RE: [Patch, microblaze]: Add optimized lshrsi3
Hi Michael, -Original Message- From: Michael Eager [mailto:ea...@eagerm.com] Sent: Sunday, 9 February 2014 2:58 am To: David Holsgrove; gcc-patches@gcc.gnu.org Cc: Edgar Iglesias; John Williams; Vidhumouli Hunsigida; Nagaraju Mekala Subject: Re: [Patch, microblaze]: Add optimized lshrsi3 On 11/25/13 23:53, David Holsgrove wrote: Add optimized lshrsi3 instruction, to be used when optimizing for size with immediate values over 5 Changelog 2013-11-26 Nagaraju Mekala nagaraju.mek...@xilinx.com * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn. David -- Please put the description of the patch in the text of the email, rather than hiding it within an attached patch. The patch describes a very specific situation where this patch will have an effect. Please provide a test case. Updated version of patch attached with testcase. New Changelog entries are; Changelog 2013-11-26 David Holsgrove david.holsgr...@xilinx.com * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn ChangeLog/testsuite 2014-02-12 David Holsgrove david.holsgr...@xilinx.com * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test. thanks, David -- Michael Eager ea...@eagercon.com 1960 Park Blvd., Palo Alto, CA 94306 650-325-8077 0003-Patch-microblaze-Add-optimized-lshrsi3.patch Description: 0003-Patch-microblaze-Add-optimized-lshrsi3.patch
Re: [Patch, microblaze]: Add optimized lshrsi3
On 11/25/13 23:53, David Holsgrove wrote: Add optimized lshrsi3 instruction, to be used when optimizing for size with immediate values over 5 Changelog 2013-11-26 Nagaraju Mekala nagaraju.mek...@xilinx.com * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn. David -- Please put the description of the patch in the text of the email, rather than hiding it within an attached patch. The patch describes a very specific situation where this patch will have an effect. Please provide a test case. -- Michael Eagerea...@eagercon.com 1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
