RE: [Patch] Fix for MIPS PR target/65604

[Moore, Catherine]

> -Original Message-
> From: Steve Ellcey [mailto:sell...@imgtec.com]
> Sent: Tuesday, December 15, 2015 4:09 PM
> To: Moore, Catherine
> Cc: gcc-patches@gcc.gnu.org; matthew.fort...@imgtec.com
> Subject: RE: [Patch] Fix for MIPS PR target/65604
> 
> On Tue, 2015-12-15 at 15:13 +, Moore, Catherine wrote:
> 
> >
> > HI Steve, The patch is OK.  Will you please add a test case and repost?
> > Thanks,
> > Catherine
> 
> Here is the patch with a test case.
> 

Looks good, thanks.

RE: [Patch] Fix for MIPS PR target/65604

[Steve Ellcey]

On Tue, 2015-12-15 at 15:13 +, Moore, Catherine wrote:

> 
> HI Steve, The patch is OK.  Will you please add a test case and repost?
> Thanks,
> Catherine

Here is the patch with a test case.

2015-12-15  Steve Ellcey  

PR target/65604
* config/mips/mips.c (mips_output_division): Check flag_delayed_branch.


diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 6145944..8444a91 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -13687,9 +13687,17 @@ mips_output_division (const char *division, rtx 
*operands)
}
   else
{
- output_asm_insn ("%(bne\t%2,%.,1f", operands);
- output_asm_insn (s, operands);
- s = "break\t7%)\n1:";
+ if (flag_delayed_branch)
+   {
+ output_asm_insn ("%(bne\t%2,%.,1f", operands);
+ output_asm_insn (s, operands);
+ s = "break\t7%)\n1:";
+   }
+ else
+   {
+ output_asm_insn (s, operands);
+ s = "bne\t%2,%.,1f\n\tnop\n\tbreak\t7\n1:";
+   }
}
 }
   return s;



2015-12-15  Steve Ellcey  

PR target/65604
* gcc.target/mips/div-delay.c: New test.


diff --git a/gcc/testsuite/gcc.target/mips/div-delay.c 
b/gcc/testsuite/gcc.target/mips/div-delay.c
index e69de29..bdeb125 100644
--- a/gcc/testsuite/gcc.target/mips/div-delay.c
+++ b/gcc/testsuite/gcc.target/mips/div-delay.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=mips1 -fno-delayed-branch" } */
+/* { dg-final { scan-assembler "\tbne\t.*\tnop" } } */
+
+/* Ensure that mips1 does not put anything in the delay slot of the bne
+   instruction when checking for divide by zero.  mips2+ systems use teq
+   instead of bne and teq has no delay slot.  */
+
+NOCOMPRESSION int
+foo (int a, int b)
+{
+  return a / b;
+}

RE: [Patch] Fix for MIPS PR target/65604

[Moore, Catherine]

> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Steve Ellcey
> Sent: Wednesday, December 09, 2015 1:34 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Moore, Catherine; matthew.fort...@imgtec.com
> Subject: [Patch] Fix for MIPS PR target/65604
> 
> This is a MIPS patch to make mips_output_division obey the -fno-delayed-
> branch flag.  Right now, with mips1 and -mcheck-zero-division, the division
> instruction is put into the bne delay slot even when -fno-delayed-branch is
> specified.  This change uses a similar strategy to MIPS16 where we do the
> division first and then do the zero test while the division is being 
> calculated.
> Tested with mips1 runs and by inspecting the code that is output.
> 
> OK to checkin?
> 
> Steve Ellcey
> sell...@imgtec.com
> 
> 
> 2015-12-09  Steve Ellcey  <sell...@imgtec.com>
> 
>   PR target/65604
>   * config/mips/mips.c (mips_output_division): Check
> flag_delayed_branch.
> 

HI Steve, The patch is OK.  Will you please add a test case and repost?
Thanks,
Catherine

[Patch] Fix for MIPS PR target/65604

[Steve Ellcey]

This is a MIPS patch to make mips_output_division obey the
-fno-delayed-branch flag.  Right now, with mips1 and -mcheck-zero-division,
the division instruction is put into the bne delay slot even when
-fno-delayed-branch is specified.  This change uses a similar strategy
to MIPS16 where we do the division first and then do the zero test
while the division is being calculated.  Tested with mips1 runs and by
inspecting the code that is output.

OK to checkin?

Steve Ellcey
sell...@imgtec.com


2015-12-09  Steve Ellcey  

PR target/65604
* config/mips/mips.c (mips_output_division): Check flag_delayed_branch.


diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 6145944..8444a91 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -13687,9 +13687,17 @@ mips_output_division (const char *division, rtx 
*operands)
}
   else
{
- output_asm_insn ("%(bne\t%2,%.,1f", operands);
- output_asm_insn (s, operands);
- s = "break\t7%)\n1:";
+ if (flag_delayed_branch)
+   {
+ output_asm_insn ("%(bne\t%2,%.,1f", operands);
+ output_asm_insn (s, operands);
+ s = "break\t7%)\n1:";
+   }
+ else
+   {
+ output_asm_insn (s, operands);
+ s = "bne\t%2,%.,1f\n\tnop\n\tbreak\t7\n1:";
+   }
}
 }
   return s;