Re: [Patch 1/2][ARM]Split insn type alu_reg into alu_sreg and alu_dsp_reg
On 10/07/14 08:46, Terry Guo wrote: Hi there, Currently the insn type of DSP-kind instructions like QSUB8 is alu_reg which is same as other normal instructions like SUB. In order to distinguish those DSP-kind instructions, this patch intends to replace current alu_reg with two sub categories alu_sreg and alu_dsp_reg. Meanwhile the alus_reg is renamed to alus_sreg in terms of consistence. This is the first patch of this series and intends to cover the files under gcc/config/arm. Tested with gcc regression, no new regressions. Is it ok to trunk? BR, Terry This is OK. But please wait for the review of the AArch64 code before committing (both patches need to be in one commit for consistency). R. 2014-07-10 Terry Guo terry@arm.com * config/arm/types.md (alu_reg): Replaced by alu_sreg and alu_dsp_reg. (alus_reg): Renamed to alus_sreg. * config/arm/arm-fixed.md: Change type of non-dsp instructions from alu_reg to alu_sreg. Change type of dsp instructions from alu_reg to alu_dsp_reg. * config/arm/thumb1.md: Likewise. * config/arm/thumb2.md: Likewise. * config/arm/arm.c (cortexa7_older_only): Use new ALU type names. * config/arm/arm1020e.md (1020alu_op): Replace alu_reg and alus_reg with alu_sreg and alus_sreg. * config/arm/arm1026ejs.md (alu_op): Likewise. * config/arm/arm1136jfs.md (11_alu_op): Likewise. * config/arm/arm926ejs.md (9_alu_op): Likewise. * config/arm/fa526.md (526_alu_op): Likewise. * config/arm/fa606te.md (606te_alu_op): Likewise. * config/arm/fa626te.md (626te_alu_op): Likewise. * config/arm/fa726te.md (726te_alu_op): Likewise. * config/arm/fmp626.md (mp626_alu_op): Likewise. * config/arm/arm.md (core_cycles): Replace alu_reg and alus_reg with alu_sreg, alu_dsp_reg and alus_sreg. * config/arm/cortex-a15.md (cortex_a15_alu): Likewise. * config/arm/cortex-a5.md (cortex_a5_alu): Likewise. * config/arm/cortex-a53.md (cortex_a53_alu): Likewise. * config/arm/cortex-a7.md (cortex_a7_alu_sreg): Likewise. * config/arm/cortex-a8.md (cortex_a8_alu): Likewise. * config/arm/cortex-a9.md (cortex_a9_dp): Likewise. * config/arm/cortex-m4.md (cortex_m4_alu): Likewise. * config/arm/cortex-r4.md (cortex_r4_alu): Likewise. * config/arm/marvell-pj4.md (pj4_alu, pj4_alu_conds): Likewise. arm-new-insn-type-v3.txt diff --git a/gcc/config/arm/arm-fixed.md b/gcc/config/arm/arm-fixed.md index 4ab9d35..5611ad1 100644 --- a/gcc/config/arm/arm-fixed.md +++ b/gcc/config/arm/arm-fixed.md @@ -26,7 +26,7 @@ add%?\\t%0, %1, %2 [(set_attr predicable yes) (set_attr predicable_short_it yes,no) - (set_attr type alu_reg)]) + (set_attr type alu_sreg)]) (define_insn addmode3 [(set (match_operand:ADDSUB 0 s_register_operand =r) @@ -36,7 +36,7 @@ saddqaddsub_suf%?\\t%0, %1, %2 [(set_attr predicable yes) (set_attr predicable_short_it no) - (set_attr type alu_reg)]) + (set_attr type alu_dsp_reg)]) (define_insn usaddmode3 [(set (match_operand:UQADDSUB 0 s_register_operand =r) @@ -46,7 +46,7 @@ uqaddqaddsub_suf%?\\t%0, %1, %2 [(set_attr predicable yes) (set_attr predicable_short_it no) - (set_attr type alu_reg)]) + (set_attr type alu_dsp_reg)]) (define_insn ssaddmode3 [(set (match_operand:QADDSUB 0 s_register_operand =r) @@ -56,7 +56,7 @@ qaddqaddsub_suf%?\\t%0, %1, %2 [(set_attr predicable yes) (set_attr predicable_short_it no) - (set_attr type alu_reg)]) + (set_attr type alu_dsp_reg)]) (define_insn submode3 [(set (match_operand:FIXED 0 s_register_operand =l,r) @@ -66,7 +66,7 @@ sub%?\\t%0, %1, %2 [(set_attr predicable yes) (set_attr predicable_short_it yes,no) - (set_attr type alu_reg)]) + (set_attr type alu_sreg)]) (define_insn submode3 [(set (match_operand:ADDSUB 0 s_register_operand =r) @@ -76,7 +76,7 @@ ssubqaddsub_suf%?\\t%0, %1, %2 [(set_attr predicable yes) (set_attr predicable_short_it no) - (set_attr type alu_reg)]) + (set_attr type alu_dsp_reg)]) (define_insn ussubmode3 [(set (match_operand:UQADDSUB 0 s_register_operand =r) @@ -87,7 +87,7 @@ uqsubqaddsub_suf%?\\t%0, %1, %2 [(set_attr predicable yes) (set_attr predicable_short_it no) - (set_attr type alu_reg)]) + (set_attr type alu_dsp_reg)]) (define_insn sssubmode3 [(set (match_operand:QADDSUB 0 s_register_operand =r) @@ -97,7 +97,7 @@ qsubqaddsub_suf%?\\t%0, %1, %2 [(set_attr predicable yes) (set_attr predicable_short_it no) - (set_attr type alu_reg)]) + (set_attr type alu_dsp_reg)]) ;; Fractional multiplies. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 78cae73..942df7d 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -11710,8 +11710,9 @@ cortexa7_older_only (rtx insn) switch (get_attr_type
[Patch 1/2][ARM]Split insn type alu_reg into alu_sreg and alu_dsp_reg
Hi there,
Currently the insn type of DSP-kind instructions like QSUB8 is alu_reg which
is same as other normal instructions like SUB. In order to distinguish those
DSP-kind instructions, this patch intends to replace current alu_reg with
two sub categories alu_sreg and alu_dsp_reg. Meanwhile the alus_reg is
renamed to alus_sreg in terms of consistence. This is the first patch of
this series and intends to cover the files under gcc/config/arm. Tested with
gcc regression, no new regressions. Is it ok to trunk?
BR,
Terry
2014-07-10 Terry Guo terry@arm.com
* config/arm/types.md (alu_reg): Replaced by alu_sreg and alu_dsp_reg.
(alus_reg): Renamed to alus_sreg.
* config/arm/arm-fixed.md: Change type of non-dsp instructions
from alu_reg to alu_sreg. Change type of dsp instructions from
alu_reg to alu_dsp_reg.
* config/arm/thumb1.md: Likewise.
* config/arm/thumb2.md: Likewise.
* config/arm/arm.c (cortexa7_older_only): Use new ALU type names.
* config/arm/arm1020e.md (1020alu_op): Replace alu_reg and alus_reg
with
alu_sreg and alus_sreg.
* config/arm/arm1026ejs.md (alu_op): Likewise.
* config/arm/arm1136jfs.md (11_alu_op): Likewise.
* config/arm/arm926ejs.md (9_alu_op): Likewise.
* config/arm/fa526.md (526_alu_op): Likewise.
* config/arm/fa606te.md (606te_alu_op): Likewise.
* config/arm/fa626te.md (626te_alu_op): Likewise.
* config/arm/fa726te.md (726te_alu_op): Likewise.
* config/arm/fmp626.md (mp626_alu_op): Likewise.
* config/arm/arm.md (core_cycles): Replace alu_reg and alus_reg with
alu_sreg, alu_dsp_reg and alus_sreg.
* config/arm/cortex-a15.md (cortex_a15_alu): Likewise.
* config/arm/cortex-a5.md (cortex_a5_alu): Likewise.
* config/arm/cortex-a53.md (cortex_a53_alu): Likewise.
* config/arm/cortex-a7.md (cortex_a7_alu_sreg): Likewise.
* config/arm/cortex-a8.md (cortex_a8_alu): Likewise.
* config/arm/cortex-a9.md (cortex_a9_dp): Likewise.
* config/arm/cortex-m4.md (cortex_m4_alu): Likewise.
* config/arm/cortex-r4.md (cortex_r4_alu): Likewise.
* config/arm/marvell-pj4.md (pj4_alu, pj4_alu_conds): Likewise.diff --git a/gcc/config/arm/arm-fixed.md b/gcc/config/arm/arm-fixed.md
index 4ab9d35..5611ad1 100644
--- a/gcc/config/arm/arm-fixed.md
+++ b/gcc/config/arm/arm-fixed.md
@@ -26,7 +26,7 @@
add%?\\t%0, %1, %2
[(set_attr predicable yes)
(set_attr predicable_short_it yes,no)
- (set_attr type alu_reg)])
+ (set_attr type alu_sreg)])
(define_insn addmode3
[(set (match_operand:ADDSUB 0 s_register_operand =r)
@@ -36,7 +36,7 @@
saddqaddsub_suf%?\\t%0, %1, %2
[(set_attr predicable yes)
(set_attr predicable_short_it no)
- (set_attr type alu_reg)])
+ (set_attr type alu_dsp_reg)])
(define_insn usaddmode3
[(set (match_operand:UQADDSUB 0 s_register_operand =r)
@@ -46,7 +46,7 @@
uqaddqaddsub_suf%?\\t%0, %1, %2
[(set_attr predicable yes)
(set_attr predicable_short_it no)
- (set_attr type alu_reg)])
+ (set_attr type alu_dsp_reg)])
(define_insn ssaddmode3
[(set (match_operand:QADDSUB 0 s_register_operand =r)
@@ -56,7 +56,7 @@
qaddqaddsub_suf%?\\t%0, %1, %2
[(set_attr predicable yes)
(set_attr predicable_short_it no)
- (set_attr type alu_reg)])
+ (set_attr type alu_dsp_reg)])
(define_insn submode3
[(set (match_operand:FIXED 0 s_register_operand =l,r)
@@ -66,7 +66,7 @@
sub%?\\t%0, %1, %2
[(set_attr predicable yes)
(set_attr predicable_short_it yes,no)
- (set_attr type alu_reg)])
+ (set_attr type alu_sreg)])
(define_insn submode3
[(set (match_operand:ADDSUB 0 s_register_operand =r)
@@ -76,7 +76,7 @@
ssubqaddsub_suf%?\\t%0, %1, %2
[(set_attr predicable yes)
(set_attr predicable_short_it no)
- (set_attr type alu_reg)])
+ (set_attr type alu_dsp_reg)])
(define_insn ussubmode3
[(set (match_operand:UQADDSUB 0 s_register_operand =r)
@@ -87,7 +87,7 @@
uqsubqaddsub_suf%?\\t%0, %1, %2
[(set_attr predicable yes)
(set_attr predicable_short_it no)
- (set_attr type alu_reg)])
+ (set_attr type alu_dsp_reg)])
(define_insn sssubmode3
[(set (match_operand:QADDSUB 0 s_register_operand =r)
@@ -97,7 +97,7 @@
qsubqaddsub_suf%?\\t%0, %1, %2
[(set_attr predicable yes)
(set_attr predicable_short_it no)
- (set_attr type alu_reg)])
+ (set_attr type alu_dsp_reg)])
;; Fractional multiplies.
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 78cae73..942df7d 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -11710,8 +11710,9 @@ cortexa7_older_only (rtx insn)
switch (get_attr_type (insn))
{
-case TYPE_ALU_REG:
-case TYPE_ALUS_REG:
+case TYPE_ALU_DSP_REG:
+case TYPE_ALU_SREG:
+case TYPE_ALUS_SREG:
case TYPE_LOGIC_REG:
case TYPE_LOGICS_REG:
case TYPE_ADC_REG:
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index d6ca79a..114a2fa 100644
--- a/gcc/config/arm/arm.md
+++
