Re: [Patch 2/2][AArch64]Split insn type alu_reg into alu_sreg and alu_dsp_reg

2014-07-11 Thread Richard Earnshaw 
On 10/07/14 09:06, Terry Guo wrote:
 Hi there,
 
 As the second and final patch in this series, it intends to update alu_reg
 and alus_reg types for AArch64 port. With this change, the gcc can be
 successfully built for AArch64. Is it OK to trunk?
 
 BR,
 Terry
 
 2014-07-10  Terry Guo  terry@arm.com
 
  * config/aarch64/aarch64.md (*addsi3_aarch64, *addsi3_aarch64_uxtw,
  subsi3, *adddi3_aarch64, *subsi3_uxtw, subdi3, absdi2, negmode2,
  add_losym_mode, *negsi2_uxtw, tlsle_small_mode): Rename type
 alu_reg
  to alu_sreg. 
  (addmode3_compare0, *addsi3_compare0_uxtw, *addmode3nr_compare0,
  submode3_compare0, *compare_negmode, *negmode2_compare0,
  subsi3_compare0_uxtw, *negsi2_compare0_uxtw, *cmpmode): Rename type 
  alus_reg to alus_sreg.
 
 

OK.  As mentioned in the other thread, please commit both patches in a
single commit.

R.

 aarch64-new-insn-type-v1.txt
 
 
 diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
 index 3eb783c..76d8cd3 100644
 --- a/gcc/config/aarch64/aarch64.md
 +++ b/gcc/config/aarch64/aarch64.md
 @@ -1167,7 +1167,7 @@
add\\t%w0, %w1, %w2
add\\t%0.2s, %1.2s, %2.2s
sub\\t%w0, %w1, #%n2
 -  [(set_attr type alu_imm,alu_reg,neon_add,alu_imm)
 +  [(set_attr type alu_imm,alu_sreg,neon_add,alu_imm)
 (set_attr simd *,*,yes,*)]
  )
  
 @@ -1183,7 +1183,7 @@
add\\t%w0, %w1, %2
add\\t%w0, %w1, %w2
sub\\t%w0, %w1, #%n2
 -  [(set_attr type alu_imm,alu_reg,alu_imm)]
 +  [(set_attr type alu_imm,alu_sreg,alu_imm)]
  )
  
  (define_insn *adddi3_aarch64
 @@ -1198,7 +1198,7 @@
add\\t%x0, %x1, %x2
sub\\t%x0, %x1, #%n2
add\\t%d0, %d1, %d2
 -  [(set_attr type alu_imm,alu_reg,alu_imm,alu_reg)
 +  [(set_attr type alu_imm,alu_sreg,alu_imm,alu_sreg)
 (set_attr simd *,*,*,yes)]
  )
  
 @@ -1234,7 +1234,7 @@
adds\\t%w0, %w1, %w2
adds\\t%w0, %w1, %w2
subs\\t%w0, %w1, #%n2
 -  [(set_attr type alus_reg,alus_imm,alus_imm)]
 +  [(set_attr type alus_sreg,alus_imm,alus_imm)]
  )
  
  ;; zero_extend version of above
 @@ -1251,7 +1251,7 @@
adds\\t%w0, %w1, %w2
adds\\t%w0, %w1, %w2
subs\\t%w0, %w1, #%n2
 -  [(set_attr type alus_reg,alus_imm,alus_imm)]
 +  [(set_attr type alus_sreg,alus_imm,alus_imm)]
  )
  
  (define_insn *adds_mul_imm_mode
 @@ -1365,7 +1365,7 @@
cmn\\t%w0, %w1
cmn\\t%w0, %w1
cmp\\t%w0, #%n1
 -  [(set_attr type alus_reg,alus_imm,alus_imm)]
 +  [(set_attr type alus_sreg,alus_imm,alus_imm)]
  )
  
  (define_insn *compare_negmode
 @@ -1375,7 +1375,7 @@
(match_operand:GPI 1 register_operand r)))]

cmn\\t%w1, %w0
 -  [(set_attr type alus_reg)]
 +  [(set_attr type alus_sreg)]
  )
  
  (define_insn *add_shift_mode
 @@ -1647,7 +1647,7 @@
  (match_operand:SI 2 register_operand r)))]

sub\\t%w0, %w1, %w2
 -  [(set_attr type alu_reg)]
 +  [(set_attr type alu_sreg)]
  )
  
  ;; zero_extend version of above
 @@ -1658,7 +1658,7 @@
  (match_operand:SI 2 register_operand r]

sub\\t%w0, %w1, %w2
 -  [(set_attr type alu_reg)]
 +  [(set_attr type alu_sreg)]
  )
  
  (define_insn subdi3
 @@ -1669,7 +1669,7 @@
@
 sub\\t%x0, %x1, %x2
 sub\\t%d0, %d1, %d2
 -  [(set_attr type alu_reg, neon_sub)
 +  [(set_attr type alu_sreg, neon_sub)
 (set_attr simd *,yes)]
  )
  
 @@ -1701,7 +1701,7 @@
   (minus:GPI (match_dup 1) (match_dup 2)))]

subs\\t%w0, %w1, %w2
 -  [(set_attr type alus_reg)]
 +  [(set_attr type alus_sreg)]
  )
  
  ;; zero_extend version of above
 @@ -1714,7 +1714,7 @@
   (zero_extend:DI (minus:SI (match_dup 1) (match_dup 2]

subs\\t%w0, %w1, %w2
 -  [(set_attr type alus_reg)]
 +  [(set_attr type alus_sreg)]
  )
  
  (define_insn *sub_shift_mode
 @@ -1925,7 +1925,7 @@
GEN_INT (63);
  DONE;
}
 -  [(set_attr type alu_reg)]
 +  [(set_attr type alu_sreg)]
  )
  
  (define_insn negmode2
 @@ -1935,7 +1935,7 @@
@
 neg\\t%w0, %w1
 neg\\t%rtn0vas, %rtn1vas
 -  [(set_attr type alu_reg, neon_negq)
 +  [(set_attr type alu_sreg, neon_negq)
 (set_attr simd *,yes)]
  )
  
 @@ -1945,7 +1945,7 @@
   (zero_extend:DI (neg:SI (match_operand:SI 1 register_operand r]

neg\\t%w0, %w1
 -  [(set_attr type alu_reg)]
 +  [(set_attr type alu_sreg)]
  )
  
  (define_insn *ngcmode
 @@ -1975,7 +1975,7 @@
   (neg:GPI (match_dup 1)))]

negs\\t%w0, %w1
 -  [(set_attr type alus_reg)]
 +  [(set_attr type alus_sreg)]
  )
  
  ;; zero_extend version of above
 @@ -1987,7 +1987,7 @@
   (zero_extend:DI (neg:SI (match_dup 1]

negs\\t%w0, %w1
 -  [(set_attr type alus_reg)]
 +  [(set_attr type alus_sreg)]
  )
  
  (define_insn *neg_shiftmode3_compare0
 @@ -2266,7 +2266,7 @@
 cmp\\t%w0, %w1
 cmp\\t%w0, %w1
 cmn\\t%w0, #%n1
 -  [(set_attr type alus_reg,alus_imm,alus_imm)]
 +  [(set_attr type alus_sreg,alus_imm,alus_imm)]
  )
  
  (define_insn *cmpmode
 @@ -3790,7

[Patch 2/2][AArch64]Split insn type alu_reg into alu_sreg and alu_dsp_reg

2014-07-10 Thread Terry Guo 
Hi there,

As the second and final patch in this series, it intends to update alu_reg
and alus_reg types for AArch64 port. With this change, the gcc can be
successfully built for AArch64. Is it OK to trunk?

BR,
Terry

2014-07-10  Terry Guo  terry@arm.com

 * config/aarch64/aarch64.md (*addsi3_aarch64, *addsi3_aarch64_uxtw,
 subsi3, *adddi3_aarch64, *subsi3_uxtw, subdi3, absdi2, negmode2,
 add_losym_mode, *negsi2_uxtw, tlsle_small_mode): Rename type
alu_reg
 to alu_sreg. 
 (addmode3_compare0, *addsi3_compare0_uxtw, *addmode3nr_compare0,
 submode3_compare0, *compare_negmode, *negmode2_compare0,
 subsi3_compare0_uxtw, *negsi2_compare0_uxtw, *cmpmode): Rename type 
 alus_reg to alus_sreg.diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 3eb783c..76d8cd3 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1167,7 +1167,7 @@
   add\\t%w0, %w1, %w2
   add\\t%0.2s, %1.2s, %2.2s
   sub\\t%w0, %w1, #%n2
-  [(set_attr type alu_imm,alu_reg,neon_add,alu_imm)
+  [(set_attr type alu_imm,alu_sreg,neon_add,alu_imm)
(set_attr simd *,*,yes,*)]
 )
 
@@ -1183,7 +1183,7 @@
   add\\t%w0, %w1, %2
   add\\t%w0, %w1, %w2
   sub\\t%w0, %w1, #%n2
-  [(set_attr type alu_imm,alu_reg,alu_imm)]
+  [(set_attr type alu_imm,alu_sreg,alu_imm)]
 )
 
 (define_insn *adddi3_aarch64
@@ -1198,7 +1198,7 @@
   add\\t%x0, %x1, %x2
   sub\\t%x0, %x1, #%n2
   add\\t%d0, %d1, %d2
-  [(set_attr type alu_imm,alu_reg,alu_imm,alu_reg)
+  [(set_attr type alu_imm,alu_sreg,alu_imm,alu_sreg)
(set_attr simd *,*,*,yes)]
 )
 
@@ -1234,7 +1234,7 @@
   adds\\t%w0, %w1, %w2
   adds\\t%w0, %w1, %w2
   subs\\t%w0, %w1, #%n2
-  [(set_attr type alus_reg,alus_imm,alus_imm)]
+  [(set_attr type alus_sreg,alus_imm,alus_imm)]
 )
 
 ;; zero_extend version of above
@@ -1251,7 +1251,7 @@
   adds\\t%w0, %w1, %w2
   adds\\t%w0, %w1, %w2
   subs\\t%w0, %w1, #%n2
-  [(set_attr type alus_reg,alus_imm,alus_imm)]
+  [(set_attr type alus_sreg,alus_imm,alus_imm)]
 )
 
 (define_insn *adds_mul_imm_mode
@@ -1365,7 +1365,7 @@
   cmn\\t%w0, %w1
   cmn\\t%w0, %w1
   cmp\\t%w0, #%n1
-  [(set_attr type alus_reg,alus_imm,alus_imm)]
+  [(set_attr type alus_sreg,alus_imm,alus_imm)]
 )
 
 (define_insn *compare_negmode
@@ -1375,7 +1375,7 @@
 (match_operand:GPI 1 register_operand r)))]
   
   cmn\\t%w1, %w0
-  [(set_attr type alus_reg)]
+  [(set_attr type alus_sreg)]
 )
 
 (define_insn *add_shift_mode
@@ -1647,7 +1647,7 @@
   (match_operand:SI 2 register_operand r)))]
   
   sub\\t%w0, %w1, %w2
-  [(set_attr type alu_reg)]
+  [(set_attr type alu_sreg)]
 )
 
 ;; zero_extend version of above
@@ -1658,7 +1658,7 @@
   (match_operand:SI 2 register_operand r]
   
   sub\\t%w0, %w1, %w2
-  [(set_attr type alu_reg)]
+  [(set_attr type alu_sreg)]
 )
 
 (define_insn subdi3
@@ -1669,7 +1669,7 @@
   @
sub\\t%x0, %x1, %x2
sub\\t%d0, %d1, %d2
-  [(set_attr type alu_reg, neon_sub)
+  [(set_attr type alu_sreg, neon_sub)
(set_attr simd *,yes)]
 )
 
@@ -1701,7 +1701,7 @@
(minus:GPI (match_dup 1) (match_dup 2)))]
   
   subs\\t%w0, %w1, %w2
-  [(set_attr type alus_reg)]
+  [(set_attr type alus_sreg)]
 )
 
 ;; zero_extend version of above
@@ -1714,7 +1714,7 @@
(zero_extend:DI (minus:SI (match_dup 1) (match_dup 2]
   
   subs\\t%w0, %w1, %w2
-  [(set_attr type alus_reg)]
+  [(set_attr type alus_sreg)]
 )
 
 (define_insn *sub_shift_mode
@@ -1925,7 +1925,7 @@
 GEN_INT (63);
 DONE;
   }
-  [(set_attr type alu_reg)]
+  [(set_attr type alu_sreg)]
 )
 
 (define_insn negmode2
@@ -1935,7 +1935,7 @@
   @
neg\\t%w0, %w1
neg\\t%rtn0vas, %rtn1vas
-  [(set_attr type alu_reg, neon_negq)
+  [(set_attr type alu_sreg, neon_negq)
(set_attr simd *,yes)]
 )
 
@@ -1945,7 +1945,7 @@
(zero_extend:DI (neg:SI (match_operand:SI 1 register_operand r]
   
   neg\\t%w0, %w1
-  [(set_attr type alu_reg)]
+  [(set_attr type alu_sreg)]
 )
 
 (define_insn *ngcmode
@@ -1975,7 +1975,7 @@
(neg:GPI (match_dup 1)))]
   
   negs\\t%w0, %w1
-  [(set_attr type alus_reg)]
+  [(set_attr type alus_sreg)]
 )
 
 ;; zero_extend version of above
@@ -1987,7 +1987,7 @@
(zero_extend:DI (neg:SI (match_dup 1]
   
   negs\\t%w0, %w1
-  [(set_attr type alus_reg)]
+  [(set_attr type alus_sreg)]
 )
 
 (define_insn *neg_shiftmode3_compare0
@@ -2266,7 +2266,7 @@
cmp\\t%w0, %w1
cmp\\t%w0, %w1
cmn\\t%w0, #%n1
-  [(set_attr type alus_reg,alus_imm,alus_imm)]
+  [(set_attr type alus_sreg,alus_imm,alus_imm)]
 )
 
 (define_insn *cmpmode
@@ -3790,7 +3790,7 @@
  (match_operand 2 aarch64_valid_symref S)))]
   
   add\\t%w0, %w1, :lo12:%a2
-  [(set_attr type alu_reg)]
+  [(set_attr type alu_sreg)]
 )
 
 (define_insn ldr_got_small_mode
@@ -3901,7 +3901,7 @@
   UNSPEC_GOTSMALLTLS))]
   
   add\\t%w0, %w1, #%G2\;add\\t%w0, %w0, #%L2
-  [(set_attr type