Re: [Patch AArch64] Implement Vector Permute Support
On 20 January 2014 17:33, Alex Velenko wrote: > Can someone, please, commit this patch, as I do not have permissions? > Kind regards, > Alex Committed. /Marcus
Re: [Patch AArch64] Implement Vector Permute Support
On 20/01/14 11:16, Richard Earnshaw wrote: On 20/01/14 11:15, Alex Velenko wrote: On 17/01/14 15:55, Richard Earnshaw wrote: On 16/01/14 14:43, Alex Velenko wrote: On 14/01/14 15:51, pins...@gmail.com wrote: On Jan 14, 2014, at 7:19 AM, Alex Velenko wrote: Hi, This patch turns off the vec_perm patterns for aarch64_be, this should resolve the issue highlighted here http://gcc.gnu.org/ml/gcc-patches/2014-01/msg00321.html With this patch applied, the test case provided in that link compiles without an ICE. However, the Big-Endian port is still in development. This patch exposes another known but unrelated issue with Big-Endian Large-Int modes. The patch has been tested on aarch64-none-elf and aarch64_be-none-elf resulting in five further regression due to the broken implementation of Big-Endian Large-Int modes. Kind regards, Alex Velenko gcc/ 2014-01-14 Alex Velenko * config/aarch64/aarch64-simd.md (vec_perm): Add BE check. * config/aarch64/aarch64.c (aarch64_expand_vec_perm): Add comment. gcc/testsuite/ 2014-01-14 Alex Velenko * lib/target-supports.exp (check_effective_target_vect_perm): Exclude aarch64_be. (check_effective_target_vect_perm_byte): Likewise. (check_effective_target_vect_perm_short): Likewise. I think you want to use a function to check if the target is effectively big-endian instead. Internally at Cavium, our elf compiler has big-endian multi-lib. Thanks, Andrew Hi, Here is a vec-perm patch with changes proposed previously. Little and Big-Endian tested with no additional issues appearing. Kind regards, Alex gcc/ 2014-01-16 Alex Velenko * config/aarch64/aarch64-simd.md (vec_perm): Add BE check. * config/aarch64/aarch64.c (aarch64_expand_vec_perm): Add comment. gcc/testsuite/ 2014-01-16 Alex Velenko * lib/target-supports.exp (check_effective_target_vect_perm): Exclude aarch64_be. (check_effective_target_vect_perm_byte): Likewise. (check_effective_target_vect_perm_short): Likewise. The patch is missing the hunk for aarch64.c. Hi, It is a faulty changelog entry, not patch. Should be: gcc/ 2014-01-16 Alex Velenko * config/aarch64/aarch64-simd.md (vec_perm): Add BE check. gcc/testsuite/ 2014-01-16 Alex Velenko * lib/target-supports.exp (check_effective_target_vect_perm): Exclude aarch64_be. (check_effective_target_vect_perm_byte): Likewise. (check_effective_target_vect_perm_short): Likewise. On that basis, OK. R. Can someone, please, commit this patch, as I do not have permissions? Kind regards, Alex
Re: [Patch AArch64] Implement Vector Permute Support
On 20/01/14 11:15, Alex Velenko wrote: > On 17/01/14 15:55, Richard Earnshaw wrote: >> On 16/01/14 14:43, Alex Velenko wrote: >>> On 14/01/14 15:51, pins...@gmail.com wrote: > On Jan 14, 2014, at 7:19 AM, Alex Velenko wrote: > > Hi, > > This patch turns off the vec_perm patterns for aarch64_be, this should > resolve > the issue highlighted here > http://gcc.gnu.org/ml/gcc-patches/2014-01/msg00321.html > With this patch applied, the test case provided in that link compiles > without an ICE. > > However, the Big-Endian port is still in development. This patch exposes > another known but unrelated issue with Big-Endian Large-Int modes. > > The patch has been tested on aarch64-none-elf and aarch64_be-none-elf > resulting in five > further regression due to the broken implementation of Big-Endian > Large-Int modes. > > Kind regards, > Alex Velenko > > gcc/ > > 2014-01-14 Alex Velenko > > * config/aarch64/aarch64-simd.md (vec_perm): Add BE check. > * config/aarch64/aarch64.c (aarch64_expand_vec_perm): Add comment. > > gcc/testsuite/ > > 2014-01-14 Alex Velenko > > * lib/target-supports.exp > (check_effective_target_vect_perm): Exclude aarch64_be. > (check_effective_target_vect_perm_byte): Likewise. > (check_effective_target_vect_perm_short): Likewise. I think you want to use a function to check if the target is effectively big-endian instead. Internally at Cavium, our elf compiler has big-endian multi-lib. Thanks, Andrew > > >>> >>> Hi, >>> Here is a vec-perm patch with changes proposed previously. >>> Little and Big-Endian tested with no additional issues appearing. >>> >>> Kind regards, >>> Alex >>> >>> gcc/ >>> >>> 2014-01-16 Alex Velenko >>> >>> * config/aarch64/aarch64-simd.md (vec_perm): Add BE check. >>> * config/aarch64/aarch64.c (aarch64_expand_vec_perm): Add comment. >>> >>> gcc/testsuite/ >>> >>> 2014-01-16 Alex Velenko >>> >>> * lib/target-supports.exp >>> (check_effective_target_vect_perm): Exclude aarch64_be. >>> (check_effective_target_vect_perm_byte): Likewise. >>> (check_effective_target_vect_perm_short): Likewise. >>> >> >> The patch is missing the hunk for aarch64.c. >> >> > > Hi, > It is a faulty changelog entry, not patch. > Should be: > > gcc/ > > 2014-01-16 Alex Velenko > > * config/aarch64/aarch64-simd.md (vec_perm): Add BE check. > > gcc/testsuite/ > > 2014-01-16 Alex Velenko > > * lib/target-supports.exp > (check_effective_target_vect_perm): Exclude aarch64_be. > (check_effective_target_vect_perm_byte): Likewise. > (check_effective_target_vect_perm_short): Likewise. > On that basis, OK. R.
Re: [Patch AArch64] Implement Vector Permute Support
On 17/01/14 15:55, Richard Earnshaw wrote: On 16/01/14 14:43, Alex Velenko wrote: On 14/01/14 15:51, pins...@gmail.com wrote: On Jan 14, 2014, at 7:19 AM, Alex Velenko wrote: Hi, This patch turns off the vec_perm patterns for aarch64_be, this should resolve the issue highlighted here http://gcc.gnu.org/ml/gcc-patches/2014-01/msg00321.html With this patch applied, the test case provided in that link compiles without an ICE. However, the Big-Endian port is still in development. This patch exposes another known but unrelated issue with Big-Endian Large-Int modes. The patch has been tested on aarch64-none-elf and aarch64_be-none-elf resulting in five further regression due to the broken implementation of Big-Endian Large-Int modes. Kind regards, Alex Velenko gcc/ 2014-01-14 Alex Velenko * config/aarch64/aarch64-simd.md (vec_perm): Add BE check. * config/aarch64/aarch64.c (aarch64_expand_vec_perm): Add comment. gcc/testsuite/ 2014-01-14 Alex Velenko * lib/target-supports.exp (check_effective_target_vect_perm): Exclude aarch64_be. (check_effective_target_vect_perm_byte): Likewise. (check_effective_target_vect_perm_short): Likewise. I think you want to use a function to check if the target is effectively big-endian instead. Internally at Cavium, our elf compiler has big-endian multi-lib. Thanks, Andrew Hi, Here is a vec-perm patch with changes proposed previously. Little and Big-Endian tested with no additional issues appearing. Kind regards, Alex gcc/ 2014-01-16 Alex Velenko * config/aarch64/aarch64-simd.md (vec_perm): Add BE check. * config/aarch64/aarch64.c (aarch64_expand_vec_perm): Add comment. gcc/testsuite/ 2014-01-16 Alex Velenko * lib/target-supports.exp (check_effective_target_vect_perm): Exclude aarch64_be. (check_effective_target_vect_perm_byte): Likewise. (check_effective_target_vect_perm_short): Likewise. The patch is missing the hunk for aarch64.c. Hi, It is a faulty changelog entry, not patch. Should be: gcc/ 2014-01-16 Alex Velenko * config/aarch64/aarch64-simd.md (vec_perm): Add BE check. gcc/testsuite/ 2014-01-16 Alex Velenko * lib/target-supports.exp (check_effective_target_vect_perm): Exclude aarch64_be. (check_effective_target_vect_perm_byte): Likewise. (check_effective_target_vect_perm_short): Likewise.
Re: [Patch AArch64] Implement Vector Permute Support
On 16/01/14 14:43, Alex Velenko wrote: > On 14/01/14 15:51, pins...@gmail.com wrote: >> >> >>> On Jan 14, 2014, at 7:19 AM, Alex Velenko wrote: >>> >>> Hi, >>> >>> This patch turns off the vec_perm patterns for aarch64_be, this should >>> resolve >>> the issue highlighted here >>> http://gcc.gnu.org/ml/gcc-patches/2014-01/msg00321.html >>> With this patch applied, the test case provided in that link compiles >>> without an ICE. >>> >>> However, the Big-Endian port is still in development. This patch exposes >>> another known but unrelated issue with Big-Endian Large-Int modes. >>> >>> The patch has been tested on aarch64-none-elf and aarch64_be-none-elf >>> resulting in five >>> further regression due to the broken implementation of Big-Endian Large-Int >>> modes. >>> >>> Kind regards, >>> Alex Velenko >>> >>> gcc/ >>> >>> 2014-01-14 Alex Velenko >>> >>> * config/aarch64/aarch64-simd.md (vec_perm): Add BE check. >>> * config/aarch64/aarch64.c (aarch64_expand_vec_perm): Add comment. >>> >>> gcc/testsuite/ >>> >>> 2014-01-14 Alex Velenko >>> >>> * lib/target-supports.exp >>> (check_effective_target_vect_perm): Exclude aarch64_be. >>> (check_effective_target_vect_perm_byte): Likewise. >>> (check_effective_target_vect_perm_short): Likewise. >> >> I think you want to use a function to check if the target is effectively >> big-endian instead. Internally at Cavium, our elf compiler has big-endian >> multi-lib. >> >> Thanks, >> Andrew >> >>> >>> >> > > Hi, > Here is a vec-perm patch with changes proposed previously. > Little and Big-Endian tested with no additional issues appearing. > > Kind regards, > Alex > > gcc/ > > 2014-01-16 Alex Velenko > > * config/aarch64/aarch64-simd.md (vec_perm): Add BE check. > * config/aarch64/aarch64.c (aarch64_expand_vec_perm): Add comment. > > gcc/testsuite/ > > 2014-01-16 Alex Velenko > > * lib/target-supports.exp > (check_effective_target_vect_perm): Exclude aarch64_be. > (check_effective_target_vect_perm_byte): Likewise. > (check_effective_target_vect_perm_short): Likewise. > The patch is missing the hunk for aarch64.c.
Re: [Patch AArch64] Implement Vector Permute Support
On 14/01/14 15:51, pins...@gmail.com wrote:
On Jan 14, 2014, at 7:19 AM, Alex Velenko wrote:
Hi,
This patch turns off the vec_perm patterns for aarch64_be, this should resolve
the issue highlighted here
http://gcc.gnu.org/ml/gcc-patches/2014-01/msg00321.html
With this patch applied, the test case provided in that link compiles without
an ICE.
However, the Big-Endian port is still in development. This patch exposes
another known but unrelated issue with Big-Endian Large-Int modes.
The patch has been tested on aarch64-none-elf and aarch64_be-none-elf resulting
in five
further regression due to the broken implementation of Big-Endian Large-Int
modes.
Kind regards,
Alex Velenko
gcc/
2014-01-14 Alex Velenko
* config/aarch64/aarch64-simd.md (vec_perm): Add BE check.
* config/aarch64/aarch64.c (aarch64_expand_vec_perm): Add comment.
gcc/testsuite/
2014-01-14 Alex Velenko
* lib/target-supports.exp
(check_effective_target_vect_perm): Exclude aarch64_be.
(check_effective_target_vect_perm_byte): Likewise.
(check_effective_target_vect_perm_short): Likewise.
I think you want to use a function to check if the target is effectively
big-endian instead. Internally at Cavium, our elf compiler has big-endian
multi-lib.
Thanks,
Andrew
Hi,
Here is a vec-perm patch with changes proposed previously.
Little and Big-Endian tested with no additional issues appearing.
Kind regards,
Alex
gcc/
2014-01-16 Alex Velenko
* config/aarch64/aarch64-simd.md (vec_perm): Add BE check.
* config/aarch64/aarch64.c (aarch64_expand_vec_perm): Add comment.
gcc/testsuite/
2014-01-16 Alex Velenko
* lib/target-supports.exp
(check_effective_target_vect_perm): Exclude aarch64_be.
(check_effective_target_vect_perm_byte): Likewise.
(check_effective_target_vect_perm_short): Likewise.
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index bc47a291de4b9b24d829e4dbf060fff7a321558f..43a9c5b27d78a47cf965636a03232005a4c8e7c3 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -3840,7 +3840,7 @@
(match_operand:VB 1 "register_operand")
(match_operand:VB 2 "register_operand")
(match_operand:VB 3 "register_operand")]
- "TARGET_SIMD"
+ "TARGET_SIMD && !BYTES_BIG_ENDIAN"
{
aarch64_expand_vec_perm (operands[0], operands[1],
operands[2], operands[3]);
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 159f88f28dd838d4aee6d75f8d21897695609c49..b425183c1e893c6511ba575a0cd416563c9510be 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -3436,7 +3436,8 @@ proc check_effective_target_vect_perm { } {
} else {
set et_vect_perm_saved 0
if { [is-effective-target arm_neon_ok]
- || [istarget aarch64*-*-*]
+ || ([istarget aarch64*-*-*]
+ && [is-effective-target aarch64_little_endian])
|| [istarget powerpc*-*-*]
|| [istarget spu-*-*]
|| [istarget i?86-*-*]
@@ -3464,7 +3465,8 @@ proc check_effective_target_vect_perm_byte { } {
set et_vect_perm_byte_saved 0
if { ([is-effective-target arm_neon_ok]
&& [is-effective-target arm_little_endian])
- || [istarget aarch64*-*-*]
+ || ([istarget aarch64*-*-*]
+ && [is-effective-target aarch64_little_endian])
|| [istarget powerpc*-*-*]
|| [istarget spu-*-*] } {
set et_vect_perm_byte_saved 1
@@ -3488,7 +3490,8 @@ proc check_effective_target_vect_perm_short { } {
set et_vect_perm_short_saved 0
if { ([is-effective-target arm_neon_ok]
&& [is-effective-target arm_little_endian])
- || [istarget aarch64*-*-*]
+ || ([istarget aarch64*-*-*]
+ && [is-effective-target aarch64_little_endian])
|| [istarget powerpc*-*-*]
|| [istarget spu-*-*] } {
set et_vect_perm_short_saved 1
Re: [Patch AArch64] Implement Vector Permute Support
> On Jan 14, 2014, at 7:19 AM, Alex Velenko wrote: > > Hi, > > This patch turns off the vec_perm patterns for aarch64_be, this should resolve > the issue highlighted here > http://gcc.gnu.org/ml/gcc-patches/2014-01/msg00321.html > With this patch applied, the test case provided in that link compiles without > an ICE. > > However, the Big-Endian port is still in development. This patch exposes > another known but unrelated issue with Big-Endian Large-Int modes. > > The patch has been tested on aarch64-none-elf and aarch64_be-none-elf > resulting in five > further regression due to the broken implementation of Big-Endian Large-Int > modes. > > Kind regards, > Alex Velenko > > gcc/ > > 2014-01-14 Alex Velenko > >* config/aarch64/aarch64-simd.md (vec_perm): Add BE check. >* config/aarch64/aarch64.c (aarch64_expand_vec_perm): Add comment. > > gcc/testsuite/ > > 2014-01-14 Alex Velenko > >* lib/target-supports.exp >(check_effective_target_vect_perm): Exclude aarch64_be. >(check_effective_target_vect_perm_byte): Likewise. >(check_effective_target_vect_perm_short): Likewise. I think you want to use a function to check if the target is effectively big-endian instead. Internally at Cavium, our elf compiler has big-endian multi-lib. Thanks, Andrew > >
Re: [Patch AArch64] Implement Vector Permute Support
Hi,
This patch turns off the vec_perm patterns for aarch64_be, this should
resolve
the issue highlighted here
http://gcc.gnu.org/ml/gcc-patches/2014-01/msg00321.html
With this patch applied, the test case provided in that link compiles
without an ICE.
However, the Big-Endian port is still in development. This patch exposes
another known but unrelated issue with Big-Endian Large-Int modes.
The patch has been tested on aarch64-none-elf and aarch64_be-none-elf
resulting in five
further regression due to the broken implementation of Big-Endian
Large-Int modes.
Kind regards,
Alex Velenko
gcc/
2014-01-14 Alex Velenko
* config/aarch64/aarch64-simd.md (vec_perm): Add BE check.
* config/aarch64/aarch64.c (aarch64_expand_vec_perm): Add comment.
gcc/testsuite/
2014-01-14 Alex Velenko
* lib/target-supports.exp
(check_effective_target_vect_perm): Exclude aarch64_be.
(check_effective_target_vect_perm_byte): Likewise.
(check_effective_target_vect_perm_short): Likewise.
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index bc47a291de4b9b24d829e4dbf060fff7a321558f..43a9c5b27d78a47cf965636a03232005a4c8e7c3 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -3840,7 +3840,7 @@
(match_operand:VB 1 "register_operand")
(match_operand:VB 2 "register_operand")
(match_operand:VB 3 "register_operand")]
- "TARGET_SIMD"
+ "TARGET_SIMD && !BYTES_BIG_ENDIAN"
{
aarch64_expand_vec_perm (operands[0], operands[1],
operands[2], operands[3]);
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 95360089b89d5fef2997dc6dbe7f47a6864143ea..084668af5124aa1c4a7f25495cf44b52811d0e62 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -3417,7 +3417,8 @@ proc check_effective_target_vect_perm { } {
} else {
set et_vect_perm_saved 0
if { [is-effective-target arm_neon_ok]
- || [istarget aarch64*-*-*]
+ || ([istarget aarch64*-*-*]
+ && ![istarget aarch64_be*-*-*])
|| [istarget powerpc*-*-*]
|| [istarget spu-*-*]
|| [istarget i?86-*-*]
@@ -3445,7 +3446,8 @@ proc check_effective_target_vect_perm_byte { } {
set et_vect_perm_byte_saved 0
if { ([is-effective-target arm_neon_ok]
&& [is-effective-target arm_little_endian])
- || [istarget aarch64*-*-*]
+ || ([istarget aarch64*-*-*]
+ && ![istarget aarch64_be*-*-*])
|| [istarget powerpc*-*-*]
|| [istarget spu-*-*] } {
set et_vect_perm_byte_saved 1
@@ -3469,7 +3471,8 @@ proc check_effective_target_vect_perm_short { } {
set et_vect_perm_short_saved 0
if { ([is-effective-target arm_neon_ok]
&& [is-effective-target arm_little_endian])
- || [istarget aarch64*-*-*]
+ || ([istarget aarch64*-*-*]
+ && ![istarget aarch64_be*-*-*])
|| [istarget powerpc*-*-*]
|| [istarget spu-*-*] } {
set et_vect_perm_short_saved 1
Re: [Patch AArch64] Implement Vector Permute Support
On Wed, Jan 08, 2014 at 12:10:13AM +, Andrew Pinski wrote: > On Tue, Jan 7, 2014 at 4:05 PM, Marcus Shawcroft > wrote: > > > > Andrew, We know that there are numerous issues with aarch64 BE advsimd > > support in GCC. The aarch64_be support is very much a work in progress. > > Tejas sorted out a number of fundamentals with a series of patches in > > November, notably in PCS conformance. There is more to come. However, > > aarch64_be-* support in gcc 4.9 is not going to match the level of quality > > for the aarch64-* port. > > > Yes but should not introduce an ICE while GCC is in stage3. This was > working before due not having a vec_perm before. I am going to > request this to be reverted soon if it is not fixed (the GCC rules are > clear here). Hi Andrew, I am confused, are you also proposing to revert this patch on 4.8 branch? The code has been sitting with that assert in place on trunk for well over a year (note that December 2012 was during 4.8's stage 3, not 4.9) there is no regression here. But, that doesn't absolve me of the fact that this is broken in a stupid way for big-endian AArch64. The band-aid, which I can prepare, would be to turn off vec_perm for BYTES_BIG_ENDIAN targets on the 4.9 and 4.8 branches. This is the most sensible thing to do in the short term. Naturally, you will lose vectorization of permute operations, but at least you won't get the ICE or wrong code generation. This is what the ARM back-end (from which I ported the vec_perm code) does. In the longer term you would want to audit the lane-numbering discrepancies between GCC and our architectural lane-numbers. We are some way towards that after Tejas' PCS conformance fix, but as Marcus has said, there is more to come. I should imagine that in this case you will need to provide a run-time transformation between the permute mask and an appropriate mask for tbl. To reiterate, this does not need reverted, we'll get a fix out disabling vec_perm for BYTES_BIG_ENDIAN on 4.8 branch and 4.9. Thanks, James
Re: [Patch AArch64] Implement Vector Permute Support
On Tue, Jan 7, 2014 at 4:05 PM, Marcus Shawcroft
wrote:
>
> On 7 Jan 2014, at 23:10, Andrew Pinski wrote:
>
>> On Tue, Dec 4, 2012 at 2:31 AM, James Greenhalgh
>> wrote:
>>>
>>> Hi,
>>>
>>> This patch adds support for Vector Shuffle style operations
>>> through support for TARGET_VECTORIZE_VEC_PERM_CONST_OK and
>>> the vec_perm and vec_perm_const standard patterns.
>>>
>>> In this patch we add the framework and support for the
>>> generic tbl instruction. This can be used to handle any
>>> vector permute operation, but we can do a better job for
>>> some special cases. The second patch of this series does
>>> that better job for the ZIP, UZP and TRN instructions.
>>>
>>> Is this OK to commit?
>>
>> This breaks big-endian aarch64 in a very bad way. vec_perm is
>> enabled for big-endian but aarch64_expand_vec_perm will ICE right
>> away. Can you please test big-endian also next time?
>> Here is the shortest testcase which fails at -O3:
>>
>> void fill_window(unsigned short *p, unsigned wsize)
>> {
>>unsigned n, m;
>>do {
>> m = *--p;
>> *p = (unsigned short)(m >= wsize ? m-wsize : 0);
>>} while (--n);
>> }
>>
>> This comes from zlib and it blocks my building of the trunk.
>>
>> Thanks,
>> Andrew Pinski
>>
>
> Andrew, We know that there are numerous issues with aarch64 BE advsimd
> support in GCC. The aarch64_be support is very much a work in progress.
> Tejas sorted out a number of fundamentals with a series of patches in
> November, notably in PCS conformance. There is more to come. However,
> aarch64_be-* support in gcc 4.9 is not going to match the level of quality
> for the aarch64-* port.
Yes but should not introduce an ICE while GCC is in stage3. This was
working before due not having a vec_perm before. I am going to
request this to be reverted soon if it is not fixed (the GCC rules are
clear here).
Thanks,
Andrew Pinski
PS sorry if you received this message twice, I had to remove your
company stupid message.
>
> Cheers
> /Marcus
Re: [Patch AArch64] Implement Vector Permute Support
On Tue, Dec 4, 2012 at 2:31 AM, James Greenhalgh
wrote:
>
> Hi,
>
> This patch adds support for Vector Shuffle style operations
> through support for TARGET_VECTORIZE_VEC_PERM_CONST_OK and
> the vec_perm and vec_perm_const standard patterns.
>
> In this patch we add the framework and support for the
> generic tbl instruction. This can be used to handle any
> vector permute operation, but we can do a better job for
> some special cases. The second patch of this series does
> that better job for the ZIP, UZP and TRN instructions.
>
> Is this OK to commit?
This breaks big-endian aarch64 in a very bad way. vec_perm is
enabled for big-endian but aarch64_expand_vec_perm will ICE right
away. Can you please test big-endian also next time?
Here is the shortest testcase which fails at -O3:
void fill_window(unsigned short *p, unsigned wsize)
{
unsigned n, m;
do {
m = *--p;
*p = (unsigned short)(m >= wsize ? m-wsize : 0);
} while (--n);
}
This comes from zlib and it blocks my building of the trunk.
Thanks,
Andrew Pinski
>
> Thanks,
> James Greenhalgh
>
> ---
> gcc/
>
> 2012-12-04 James Greenhalgh
>
> * config/aarch64/aarch64-protos.h
> (aarch64_split_combinev16qi): New.
> (aarch64_expand_vec_perm): Likewise.
> (aarch64_expand_vec_perm_const): Likewise.
> * config/aarch64/aarch64-simd.md (vec_perm_const): New.
> (vec_perm): Likewise.
> (aarch64_tbl1): Likewise.
> (aarch64_tbl2v16qi): Likewise.
> (aarch64_combinev16qi): New.
> * config/aarch64/aarch64.c
> (aarch64_vectorize_vec_perm_const_ok): New.
> (aarch64_split_combinev16qi): Likewise.
> (MAX_VECT_LEN): Define.
> (expand_vec_perm_d): New.
> (aarch64_expand_vec_perm_1): Likewise.
> (aarch64_expand_vec_perm): Likewise.
> (aarch64_evpc_tbl): Likewise.
> (aarch64_expand_vec_perm_const_1): Likewise.
> (aarch64_expand_vec_perm_const): Likewise.
> (aarch64_vectorize_vec_perm_const_ok): Likewise.
> (TARGET_VECTORIZE_VEC_PERM_CONST_OK): Likewise.
> * config/aarch64/iterators.md
> (unspec): Add UNSPEC_TBL, UNSPEC_CONCAT.
> (V_cmp_result): Add mapping for V2DF.
>
> gcc/testsuite/
>
> 2012-12-04 James Greenhalgh
>
> * lib/target-supports.exp
> (check_effective_target_vect_perm): Allow aarch64*-*-*.
> (check_effective_target_vect_perm_byte): Likewise.
> (check_effective_target_vect_perm_short): Likewise.
> (check_effective_target_vect_char_mult): Likewise.
> (check_effective_target_vect_extract_even_odd): Likewise.
> (check_effective_target_vect_interleave): Likewise.
RE: [Patch AArch64] Implement Vector Permute Support
> OK > > /Marcus Thanks Marcus, I've committed this and the follow-up patch to trunk and back-ported them to AArch64-4.7-branch. The back-port required back-porting the attached patch, which fixes up the expected behaviour of gcc/testsuite/gcc.dg/vect/slp-perm-8.c. After committing this as a prerequisite, the patch series regresses clean on aarch64-none-elf. Thanks, James Greenhalgh --- gcc/testsuite 2012-12-06 James Greenhalgh Backport from mainline. 2012-05-31 Greta Yorsh * lib/target-supports.exp (check_effective_target_vect_char_mult): Add arm32 to targets. * gcc.dg/vect/slp-perm-8.c (main): Prevent vectorization of the initialization loop. (dg-final): Adjust the expected number of vectorized loops depending on vect_char_mult target selector. 0001-aarch64-4.7-Backport-fix-to-gcc.dg-vect-slp-perm-8.c.patch Description: Binary data
Re: [Patch AArch64] Implement Vector Permute Support
OK /Marcus On 4 December 2012 10:31, James Greenhalgh wrote: > > Hi, > > This patch adds support for Vector Shuffle style operations > through support for TARGET_VECTORIZE_VEC_PERM_CONST_OK and > the vec_perm and vec_perm_const standard patterns. > > In this patch we add the framework and support for the > generic tbl instruction. This can be used to handle any > vector permute operation, but we can do a better job for > some special cases. The second patch of this series does > that better job for the ZIP, UZP and TRN instructions. > > Is this OK to commit? > > Thanks, > James Greenhalgh > > --- > gcc/ > > 2012-12-04 James Greenhalgh > > * config/aarch64/aarch64-protos.h > (aarch64_split_combinev16qi): New. > (aarch64_expand_vec_perm): Likewise. > (aarch64_expand_vec_perm_const): Likewise. > * config/aarch64/aarch64-simd.md (vec_perm_const): New. > (vec_perm): Likewise. > (aarch64_tbl1): Likewise. > (aarch64_tbl2v16qi): Likewise. > (aarch64_combinev16qi): New. > * config/aarch64/aarch64.c > (aarch64_vectorize_vec_perm_const_ok): New. > (aarch64_split_combinev16qi): Likewise. > (MAX_VECT_LEN): Define. > (expand_vec_perm_d): New. > (aarch64_expand_vec_perm_1): Likewise. > (aarch64_expand_vec_perm): Likewise. > (aarch64_evpc_tbl): Likewise. > (aarch64_expand_vec_perm_const_1): Likewise. > (aarch64_expand_vec_perm_const): Likewise. > (aarch64_vectorize_vec_perm_const_ok): Likewise. > (TARGET_VECTORIZE_VEC_PERM_CONST_OK): Likewise. > * config/aarch64/iterators.md > (unspec): Add UNSPEC_TBL, UNSPEC_CONCAT. > (V_cmp_result): Add mapping for V2DF. > > gcc/testsuite/ > > 2012-12-04 James Greenhalgh > > * lib/target-supports.exp > (check_effective_target_vect_perm): Allow aarch64*-*-*. > (check_effective_target_vect_perm_byte): Likewise. > (check_effective_target_vect_perm_short): Likewise. > (check_effective_target_vect_char_mult): Likewise. > (check_effective_target_vect_extract_even_odd): Likewise. > (check_effective_target_vect_interleave): Likewise.
[Patch AArch64] Implement Vector Permute Support
Hi,
This patch adds support for Vector Shuffle style operations
through support for TARGET_VECTORIZE_VEC_PERM_CONST_OK and
the vec_perm and vec_perm_const standard patterns.
In this patch we add the framework and support for the
generic tbl instruction. This can be used to handle any
vector permute operation, but we can do a better job for
some special cases. The second patch of this series does
that better job for the ZIP, UZP and TRN instructions.
Is this OK to commit?
Thanks,
James Greenhalgh
---
gcc/
2012-12-04 James Greenhalgh
* config/aarch64/aarch64-protos.h
(aarch64_split_combinev16qi): New.
(aarch64_expand_vec_perm): Likewise.
(aarch64_expand_vec_perm_const): Likewise.
* config/aarch64/aarch64-simd.md (vec_perm_const): New.
(vec_perm): Likewise.
(aarch64_tbl1): Likewise.
(aarch64_tbl2v16qi): Likewise.
(aarch64_combinev16qi): New.
* config/aarch64/aarch64.c
(aarch64_vectorize_vec_perm_const_ok): New.
(aarch64_split_combinev16qi): Likewise.
(MAX_VECT_LEN): Define.
(expand_vec_perm_d): New.
(aarch64_expand_vec_perm_1): Likewise.
(aarch64_expand_vec_perm): Likewise.
(aarch64_evpc_tbl): Likewise.
(aarch64_expand_vec_perm_const_1): Likewise.
(aarch64_expand_vec_perm_const): Likewise.
(aarch64_vectorize_vec_perm_const_ok): Likewise.
(TARGET_VECTORIZE_VEC_PERM_CONST_OK): Likewise.
* config/aarch64/iterators.md
(unspec): Add UNSPEC_TBL, UNSPEC_CONCAT.
(V_cmp_result): Add mapping for V2DF.
gcc/testsuite/
2012-12-04 James Greenhalgh
* lib/target-supports.exp
(check_effective_target_vect_perm): Allow aarch64*-*-*.
(check_effective_target_vect_perm_byte): Likewise.
(check_effective_target_vect_perm_short): Likewise.
(check_effective_target_vect_char_mult): Likewise.
(check_effective_target_vect_extract_even_odd): Likewise.
(check_effective_target_vect_interleave): Likewise.
diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index ab84257..7b72ead 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -236,4 +236,9 @@ rtx aarch64_expand_builtin (tree exp,
int ignore ATTRIBUTE_UNUSED);
tree aarch64_builtin_decl (unsigned, bool ATTRIBUTE_UNUSED);
+extern void aarch64_split_combinev16qi (rtx operands[3]);
+extern void aarch64_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel);
+extern bool
+aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel);
+
#endif /* GCC_AARCH64_PROTOS_H */
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index b3d01c1..2b0c8d6 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -3298,6 +3298,74 @@
;; Permuted-store expanders for neon intrinsics.
+;; Permute instructions
+
+;; vec_perm support
+
+(define_expand "vec_perm_const"
+ [(match_operand:VALL 0 "register_operand")
+ (match_operand:VALL 1 "register_operand")
+ (match_operand:VALL 2 "register_operand")
+ (match_operand: 3)]
+ "TARGET_SIMD"
+{
+ if (aarch64_expand_vec_perm_const (operands[0], operands[1],
+ operands[2], operands[3]))
+DONE;
+ else
+FAIL;
+})
+
+(define_expand "vec_perm"
+ [(match_operand:VB 0 "register_operand")
+ (match_operand:VB 1 "register_operand")
+ (match_operand:VB 2 "register_operand")
+ (match_operand:VB 3 "register_operand")]
+ "TARGET_SIMD"
+{
+ aarch64_expand_vec_perm (operands[0], operands[1],
+ operands[2], operands[3]);
+ DONE;
+})
+
+(define_insn "aarch64_tbl1"
+ [(set (match_operand:VB 0 "register_operand" "=w")
+ (unspec:VB [(match_operand:V16QI 1 "register_operand" "w")
+ (match_operand:VB 2 "register_operand" "w")]
+ UNSPEC_TBL))]
+ "TARGET_SIMD"
+ "tbl\\t%0., {%1.16b}, %2."
+ [(set_attr "simd_type" "simd_tbl")
+ (set_attr "simd_mode" "")]
+)
+
+;; Two source registers.
+
+(define_insn "aarch64_tbl2v16qi"
+ [(set (match_operand:V16QI 0 "register_operand" "=w")
+ (unspec:V16QI [(match_operand:OI 1 "register_operand" "w")
+ (match_operand:V16QI 2 "register_operand" "w")]
+ UNSPEC_TBL))]
+ "TARGET_SIMD"
+ "tbl\\t%0.16b, {%S1.16b - %T1.16b}, %2.16b"
+ [(set_attr "simd_type" "simd_tbl")
+ (set_attr "simd_mode" "V16QI")]
+)
+
+(define_insn_and_split "aarch64_combinev16qi"
+ [(set (match_operand:OI 0 "register_operand" "=w")
+ (unspec:OI [(match_operand:V16QI 1 "register_operand" "w")
+ (match_operand:V16QI 2 "register_operand" "w")]
+ UNSPEC_CONCAT))]
+ "TARGET_SIMD"
+ "#"
+ "&& reload_completed"
+ [(const_int 0)]
+{
+ aarch64_split_combinev16qi (operands);
+ DONE;
+})
+
(define_insn "aarch64_st2_dreg"
[(set (match_operand:TI 0 "aarch64_simd_struct_operand" "=Utv")
(unspec:TI [(match_operand:OI 1 "register_operand" "w")
diff --git a/gcc/config/aarch64/aarch64.c b
