This patch changes the split-point of 64-bit moves to after register
allocation. This means that LRA sees a simpler instruction stream, and
seems to produce better code on some testcases.
Andrew
amdgcn: Split 64-bit constant loads post-reload
This helps avoid spilling 64-bit constant loads to stack by simplifying the
code that LRA sees.
2020-04-17 Andrew Stubbs <a...@codesourcery.com>
gcc/
* config/gcn/gcn.md (*mov<mode>_insn): Only split post-reload.
diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md
index 702ba55c11a..8f5937781b2 100644
--- a/gcc/config/gcn/gcn.md
+++ b/gcc/config/gcn/gcn.md
@@ -615,9 +615,11 @@
ds_read_b64\t%0, %A1%O1\;s_waitcnt\tlgkmcnt(0)
global_load_dwordx2\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)
global_store_dwordx2\t%A0, %1%O0%g0"
- "(reload_completed && !MEM_P (operands[0]) && !MEM_P (operands[1])
- && !gcn_sgpr_move_p (operands[0], operands[1]))
- || (GET_CODE (operands[1]) == CONST_INT && !gcn_constant64_p (operands[1]))"
+ "reload_completed
+ && ((!MEM_P (operands[0]) && !MEM_P (operands[1])
+ && !gcn_sgpr_move_p (operands[0], operands[1]))
+ || (GET_CODE (operands[1]) == CONST_INT
+ && !gcn_constant64_p (operands[1])))"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 2) (match_dup 3))]
{
