Hi all,
This is the v2 patch for the wwwdocs change regarding to review.
If there is no objection, I will push this change next Tuesday.
Changes is v2:
- Remove RAO-INT from Grand Ridge
- Remove the mask register restriction for -mno-evex512
- Arrange the options alphabetically
- Other minor text change
Thx,
Haochen
Messages in v1:
This patch will mention the following changes in wwwdocs for x86_64 backend:
- AVX10.1 support
- APX EGPR, PUSH2POP2, PPX and NDD support
- Xeon Phi ISAs deprecated
Also I adjust the words in x86_64 part for GCC 13.
---
Mention AVX10.1 support, APX support and Xeon Phi deprecate in GCC 14.
Also adjust documentation in GCC 13.
---
htdocs/gcc-13/changes.html | 38 --
htdocs/gcc-14/changes.html | 27 ++-
2 files changed, 42 insertions(+), 23 deletions(-)
diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index d3bacc16..b4b1a39a 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/changes.html
@@ -543,24 +543,28 @@ You may also want to check out our
__bf16 type to x86 psABI. Users need to adjust their
AVX512BF16-related source code when upgrading GCC12 to GCC13.
- New ISA extension support for Intel AVX-IFMA was added.
- AVX-IFMA intrinsics are available via the -mavxifma
+ New ISA extension support for Intel AMX-COMPLEX was added.
+ AMX-COMPLEX intrinsics are available via the -mamx-complex
compiler switch.
- New ISA extension support for Intel AVX-VNNI-INT8 was added.
- AVX-VNNI-INT8 intrinsics are available via the -mavxvnniint8
+ New ISA extension support for Intel AMX-FP16 was added.
+ AMX-FP16 intrinsics are available via the -mamx-fp16
+ compiler switch.
+
+ New ISA extension support for Intel AVX-IFMA was added.
+ AVX-IFMA intrinsics are available via the -mavxifma
compiler switch.
New ISA extension support for Intel AVX-NE-CONVERT was added.
AVX-NE-CONVERT intrinsics are available via the
-mavxneconvert compiler switch.
- New ISA extension support for Intel CMPccXADD was added.
- CMPccXADD intrinsics are available via the -mcmpccxadd
+ New ISA extension support for Intel AVX-VNNI-INT8 was added.
+ AVX-VNNI-INT8 intrinsics are available via the -mavxvnniint8
compiler switch.
- New ISA extension support for Intel AMX-FP16 was added.
- AMX-FP16 intrinsics are available via the -mamx-fp16
+ New ISA extension support for Intel CMPccXADD was added.
+ CMPccXADD intrinsics are available via the -mcmpccxadd
compiler switch.
New ISA extension support for Intel PREFETCHI was added.
@@ -571,10 +575,6 @@ You may also want to check out our
RAO-INT intrinsics are available via the -mraoint
compiler switch.
- New ISA extension support for Intel AMX-COMPLEX was added.
- AMX-COMPLEX intrinsics are available via the -mamx-complex
- compiler switch.
-
GCC now supports the Intel CPU named Raptor Lake through
-march=raptorlake.
Raptor Lake is based on Alder Lake.
@@ -585,13 +585,13 @@ You may also want to check out our
GCC now supports the Intel CPU named Sierra Forest through
-march=sierraforest.
-The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD,
-ENQCMD and UINTR ISA extensions.
+Based on ISA extensions enabled on Alder Lake, the switch further enables
+the AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8, CMPccXADD, ENQCMD and UINTR
+ISA extensions.
GCC now supports the Intel CPU named Grand Ridge through
-march=grandridge.
-The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD,
-ENQCMD, UINTR and RAO-INT ISA extensions.
+Grand Ridge is based on Sierra Forest.
GCC now supports the Intel CPU named Emerald Rapids through
-march=emeraldrapids.
@@ -599,11 +599,13 @@ You may also want to check out our
GCC now supports the Intel CPU named Granite Rapids through
-march=graniterapids.
-The switch enables the AMX-FP16 and PREFETCHI ISA extensions.
+Based on Sapphire Rapids, the switch further enables the AMX-FP16 and
+PREFETCHI ISA extensions.
GCC now supports the Intel CPU named Granite Rapids D through
-march=graniterapids-d.
-The switch enables the AMX-FP16, PREFETCHI and AMX-COMPLEX ISA extensions.
+Based on Granite Rapids, the switch further enables the AMX-COMPLEX ISA
+extensions.
GCC now supports AMD CPUs based on the znver4 core
via -march=znver4. The switch makes GCC consider
diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index 24e6409a..4b83037a 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -320,8 +320,18 @@ a work-in-progress.
IA-32/x86-64
New compiler option -m[no-]evex512 was added.
- The compiler switch enables/disables 512 bit vector and 64 bit mask
- register. It
