This patch resolves PR target/106231 by providing insns that recognize
(zero_extend:DI (ctz:SI ...)) and (sign_extend:DI (ctz:SI ...)). The
result of ctz:SI is always between 0 and 32 (or undefined), so
sign_extension is the same as zero_extension, and the result is already
extended in the destination register.
Things are a little complicated, because the existing implementation
of *ctzsi2 handles multiple cases, including false dependencies, which
we continue to support in this patch.
This patch has been tested on x86_64-pc-linux-gnu with make bootstrap
and make -k check with no new failures. Ok for mainline?
2022-07-16 Roger Sayle
gcc/ChangeLog
PR target/106231
* config/i386/i386.md (*ctzsidi2_ext): New insn_and_split
to recognize any_extend:DI of ctz:SI which is implicitly extended.
(*ctzsidi2_ext_falsedep): New define_insn to model a DImode
extended ctz:SI that has preceding xor to break false dependency.
gcc/testsuite/ChangeLog
PR target/106231
* gcc.target/i386/pr106231-1.c: New test case.
* gcc.target/i386/pr106231-2.c: New test case.
Thanks in advance,
Roger
--
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 3b02d0c..164b0c2 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -16431,6 +16431,66 @@
(set_attr "prefix_rep" "1")
(set_attr "mode" "SI")])
+(define_insn_and_split "*ctzsidi2_ext"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (any_extend:DI
+ (ctz:SI
+ (match_operand:SI 1 "nonimmediate_operand" "rm"
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT"
+{
+ if (TARGET_BMI)
+return "tzcnt{l}\t{%1, %k0|%k0, %1}";
+ else if (TARGET_CPU_P (GENERIC)
+ && !optimize_function_for_size_p (cfun))
+/* tzcnt expands to 'rep bsf' and we can use it even if !TARGET_BMI. */
+return "rep%; bsf{l}\t{%1, %k0|%k0, %1}";
+ return "bsf{l}\t{%1, %k0|%k0, %1}";
+}
+ "(TARGET_BMI || TARGET_CPU_P (GENERIC))
+ && TARGET_AVOID_FALSE_DEP_FOR_BMI && epilogue_completed
+ && optimize_function_for_speed_p (cfun)
+ && !reg_mentioned_p (operands[0], operands[1])"
+ [(parallel
+[(set (match_dup 0)
+ (any_extend:DI (ctz:SI (match_dup 1
+ (unspec [(match_dup 0)] UNSPEC_INSN_FALSE_DEP)
+ (clobber (reg:CC FLAGS_REG))])]
+ "ix86_expand_clear (operands[0]);"
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set (attr "prefix_rep")
+ (if_then_else
+ (ior (match_test "TARGET_BMI")
+ (and (not (match_test "optimize_function_for_size_p (cfun)"))
+(match_test "TARGET_CPU_P (GENERIC)")))
+ (const_string "1")
+ (const_string "0")))
+ (set_attr "mode" "SI")])
+
+(define_insn "*ctzsidi2_ext_falsedep"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (any_extend:DI
+ (ctz:SI
+ (match_operand:SI 1 "nonimmediate_operand" "rm"
+ (unspec [(match_operand:DI 2 "register_operand" "0")]
+ UNSPEC_INSN_FALSE_DEP)
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT"
+{
+ if (TARGET_BMI)
+return "tzcnt{l}\t{%1, %k0|%k0, %1}";
+ else if (TARGET_CPU_P (GENERIC))
+/* tzcnt expands to 'rep bsf' and we can use it even if !TARGET_BMI. */
+return "rep%; bsf{l}\t{%1, %k0|%k0, %1}";
+ else
+gcc_unreachable ();
+}
+ [(set_attr "type" "alu1")
+ (set_attr "prefix_0f" "1")
+ (set_attr "prefix_rep" "1")
+ (set_attr "mode" "SI")])
+
(define_insn "bsr_rex64"
[(set (reg:CCZ FLAGS_REG)
(compare:CCZ (match_operand:DI 1 "nonimmediate_operand" "rm")
diff --git a/gcc/testsuite/gcc.target/i386/pr106231-1.c
b/gcc/testsuite/gcc.target/i386/pr106231-1.c
new file mode 100644
index 000..d17297f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr106231-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mtune=generic" } */
+long long
+foo(long long x, unsigned bits)
+{
+ return x + (unsigned) __builtin_ctz(bits);
+}
+/* { dg-final { scan-assembler-not "cltq" } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr106231-2.c
b/gcc/testsuite/gcc.target/i386/pr106231-2.c
new file mode 100644
index 000..fd3a8e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr106231-2.c
@@ -0,0 +1,8 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mtune=ivybridge" } */
+long long
+foo(long long x, unsigned bits)
+{
+ return x + (unsigned) __builtin_ctz(bits);
+}
+/* { dg-final { scan-assembler-not "cltq" } } */
