Add test from PR 83852 (was Re: Fix PR 83962)
On 09.04.2018 12:16, Andrey Belevantsev wrote:
> On 06.04.2018 18:59, Alexander Monakov wrote:
>> On Tue, 3 Apr 2018, Andrey Belevantsev wrote:
>>
>>> Hello,
>>>
>>> This issues is about the correct order in which we need to call the
>>> routines that fix up the control flow for us.
>>
>> OK with formatting both in the new comment and the Changelog fixed.
>
> Thanks, fixed that in rev. 259229.
I've found out that this patch also fixes PR 83852, so I've committed the
test from that PR as obvious after verifying that it works on cross-ppc
compiler and on x86-64.
Andrey
Index: gcc.dg/pr83852.c
===
*** gcc.dg/pr83852.c(revision 0)
--- gcc.dg/pr83852.c(revision 259373)
***
*** 0
--- 1,33
+ /* { dg-do compile { target powerpc*-*-* ia64-*-* i?86-*-* x86_64-*-* } } */
+ /* { dg-options "-std=gnu99 -O2 -fselective-scheduling -fno-if-conversion
-fno-tree-dse -w" } */
+ long long int uo;
+ unsigned int vt;
+
+ void
+ r5 (long long int h8, long long int pu)
+ {
+ short int wj;
+ long long int *mh = h8;
+
+ for (wj = 0; wj < 3; ++wj)
+ {
+ int oq;
+ long long int ns, xf;
+
+ h8 += 2;
+ oq = !!h8 && !!wj;
+ ++uo;
+ vt ^= oq + uo;
+ ns = !!uo && !!vt;
+ xf = (h8 != 0) ? mh : 1;
+ pu += ns < xf;
+ }
+
+ for (pu = 0; pu < 1; ++pu)
+ {
+ int *sc;
+
+ sc = (int *)&pu;
+ *sc = 0;
+ }
+ }
Index: ChangeLog
===
*** ChangeLog (revision 259372)
--- ChangeLog (revision 259373)
***
*** 1,3
--- 1,8
+ 2018-04-13 Andrey Belevantsev
+
+ PR rtl-optimization/83852
+ * gcc.dg/pr83852.c: New testcase.
+
2018-04-13 Andreas Krebbel
PR testsuite/85326
Re: Fix PR 83962
On 06.04.2018 18:59, Alexander Monakov wrote:
> On Tue, 3 Apr 2018, Andrey Belevantsev wrote:
>
>> Hello,
>>
>> This issues is about the correct order in which we need to call the
>> routines that fix up the control flow for us.
>
> OK with formatting both in the new comment and the Changelog fixed.
Thanks, fixed that in rev. 259229.
Andrey
>
>> Best,
>> Andrey
>>
>> 2018-04-03 Andrey Belevantsev
>>
>> PR rtl-optimization/83962
>>
>> * sel-sched-ir.c (tidy_control_flow): Correct the order in which we call
>> tidy_fallthru_edge
>> and tidy_control_flow.
>>
>> * gcc.dg/pr83962.c: New test.
>>
>> diff --git a/gcc/sel-sched-ir.c b/gcc/sel-sched-ir.c
>> index a965d2ec42f..f6de96a7f3d 100644
>> --- a/gcc/sel-sched-ir.c
>> +++ b/gcc/sel-sched-ir.c
>> @@ -3839,9 +3839,13 @@ tidy_control_flow (basic_block xbb, bool full_tidying)
>>&& INSN_SCHED_TIMES (BB_END (xbb)) == 0
>>&& !IN_CURRENT_FENCE_P (BB_END (xbb)))
>> {
>> - if (sel_remove_insn (BB_END (xbb), false, false))
>> -return true;
>> + /* We used to call sel_remove_insn here that can trigger
>> tidy_control_flow
>> + before we fix up the fallthru edge. Correct that ordering by
>> +explicitly doing the latter before the former. */
>> + clear_expr (INSN_EXPR (BB_END (xbb)));
>>tidy_fallthru_edge (EDGE_SUCC (xbb, 0));
>> + if (tidy_control_flow (xbb, false))
>> + return true;
>> }
>>
>>first = sel_bb_head (xbb);
>> diff --git a/gcc/testsuite/gcc.dg/pr83962.c b/gcc/testsuite/gcc.dg/pr83962.c
>> new file mode 100644
>> index 000..0547e218715
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.dg/pr83962.c
>> @@ -0,0 +1,10 @@
>> +/* { dg-do compile { target powerpc*-*-* ia64-*-* i?86-*-* x86_64-*-* } } */
>> +/* { dg-options "-std=gnu99 -O1 -fselective-scheduling2 -fschedule-insns2
>> -fcse-follow-jumps -fno-ssa-phiopt -fno-guess-branch-probability" } */
>> +unsigned int ca;
>> +
>> +void
>> +v6 (long long unsigned int as, int p9)
>> +{
>> + while (p9 < 1)
>> +as = (as != ca) || (as > 1);
>> +}
>>
Re: Fix PR 83962
On Tue, 3 Apr 2018, Andrey Belevantsev wrote:
> Hello,
>
> This issues is about the correct order in which we need to call the
> routines that fix up the control flow for us.
OK with formatting both in the new comment and the Changelog fixed.
> Best,
> Andrey
>
> 2018-04-03 Andrey Belevantsev
>
> PR rtl-optimization/83962
>
> * sel-sched-ir.c (tidy_control_flow): Correct the order in which we call
> tidy_fallthru_edge
> and tidy_control_flow.
>
> * gcc.dg/pr83962.c: New test.
>
> diff --git a/gcc/sel-sched-ir.c b/gcc/sel-sched-ir.c
> index a965d2ec42f..f6de96a7f3d 100644
> --- a/gcc/sel-sched-ir.c
> +++ b/gcc/sel-sched-ir.c
> @@ -3839,9 +3839,13 @@ tidy_control_flow (basic_block xbb, bool full_tidying)
>&& INSN_SCHED_TIMES (BB_END (xbb)) == 0
>&& !IN_CURRENT_FENCE_P (BB_END (xbb)))
> {
> - if (sel_remove_insn (BB_END (xbb), false, false))
> -return true;
> + /* We used to call sel_remove_insn here that can trigger
> tidy_control_flow
> + before we fix up the fallthru edge. Correct that ordering by
> +explicitly doing the latter before the former. */
> + clear_expr (INSN_EXPR (BB_END (xbb)));
>tidy_fallthru_edge (EDGE_SUCC (xbb, 0));
> + if (tidy_control_flow (xbb, false))
> + return true;
> }
>
>first = sel_bb_head (xbb);
> diff --git a/gcc/testsuite/gcc.dg/pr83962.c b/gcc/testsuite/gcc.dg/pr83962.c
> new file mode 100644
> index 000..0547e218715
> --- /dev/null
> +++ b/gcc/testsuite/gcc.dg/pr83962.c
> @@ -0,0 +1,10 @@
> +/* { dg-do compile { target powerpc*-*-* ia64-*-* i?86-*-* x86_64-*-* } } */
> +/* { dg-options "-std=gnu99 -O1 -fselective-scheduling2 -fschedule-insns2
> -fcse-follow-jumps -fno-ssa-phiopt -fno-guess-branch-probability" } */
> +unsigned int ca;
> +
> +void
> +v6 (long long unsigned int as, int p9)
> +{
> + while (p9 < 1)
> +as = (as != ca) || (as > 1);
> +}
>
Fix PR 83962
Hello,
This issues is about the correct order in which we need to call the
routines that fix up the control flow for us.
Best,
Andrey
2018-04-03 Andrey Belevantsev
PR rtl-optimization/83962
* sel-sched-ir.c (tidy_control_flow): Correct the order in which we call
tidy_fallthru_edge
and tidy_control_flow.
* gcc.dg/pr83962.c: New test.
diff --git a/gcc/sel-sched-ir.c b/gcc/sel-sched-ir.c
index a965d2ec42f..f6de96a7f3d 100644
--- a/gcc/sel-sched-ir.c
+++ b/gcc/sel-sched-ir.c
@@ -3839,9 +3839,13 @@ tidy_control_flow (basic_block xbb, bool full_tidying)
&& INSN_SCHED_TIMES (BB_END (xbb)) == 0
&& !IN_CURRENT_FENCE_P (BB_END (xbb)))
{
- if (sel_remove_insn (BB_END (xbb), false, false))
-return true;
+ /* We used to call sel_remove_insn here that can trigger
tidy_control_flow
+ before we fix up the fallthru edge. Correct that ordering by
+explicitly doing the latter before the former. */
+ clear_expr (INSN_EXPR (BB_END (xbb)));
tidy_fallthru_edge (EDGE_SUCC (xbb, 0));
+ if (tidy_control_flow (xbb, false))
+ return true;
}
first = sel_bb_head (xbb);
diff --git a/gcc/testsuite/gcc.dg/pr83962.c b/gcc/testsuite/gcc.dg/pr83962.c
new file mode 100644
index 000..0547e218715
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr83962.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target powerpc*-*-* ia64-*-* i?86-*-* x86_64-*-* } } */
+/* { dg-options "-std=gnu99 -O1 -fselective-scheduling2 -fschedule-insns2
-fcse-follow-jumps -fno-ssa-phiopt -fno-guess-branch-probability" } */
+unsigned int ca;
+
+void
+v6 (long long unsigned int as, int p9)
+{
+ while (p9 < 1)
+as = (as != ca) || (as > 1);
+}
