Re: RE: [PATCH] [X86_64]: Enable support for next generation AMD Zen5 CPU with znver5 scheduler Model

2024-03-18 Thread Jan Hubicka 
> Hello,
> 
> Le 22/02/2024 à 19:29, Anbazhagan, Karthiban a écrit :
> (...)
> >  gcc/config/i386/{znver4.md => zn4zn5.md}  | 858 +-
> 
> looks like the patch pushed to master lost the file rename.
> I get a bootstrap failure caused by the missing zn4zn5.md file.
> 
> Can you have a look?
Aha, sorry.
I did reset of the git commit since there was formatting error in
changelog.  I will fix it shortly.

Honza

Re: RE: [PATCH] [X86_64]: Enable support for next generation AMD Zen5 CPU with znver5 scheduler Model

2024-03-18 Thread Mikael Morin 

Hello,

Le 22/02/2024 à 19:29, Anbazhagan, Karthiban a écrit :
(...)

 gcc/config/i386/{znver4.md => zn4zn5.md}  | 858 +-


looks like the patch pushed to master lost the file rename.
I get a bootstrap failure caused by the missing zn4zn5.md file.

Can you have a look?

RE: [PATCH] [X86_64]: Enable support for next generation AMD Zen5 CPU with znver5 scheduler Model

2024-03-12 Thread Kumar, Venkataramanan 
[Public]

Hi Honza,

> -Original Message-
> From: Jan Hubicka 
> Sent: Tuesday, March 12, 2024 4:11 AM
> To: Anbazhagan, Karthiban 
> Cc: gcc-patches@gcc.gnu.org; Kumar, Venkataramanan
> ; Joshi, Tejas Sanjay
> ; Nagarajan, Muthu kumar raj
> ; Gopalasubramanian, Ganesh
> 
> Subject: Re: [PATCH] [X86_64]: Enable support for next generation AMD Zen5
> CPU with znver5 scheduler Model
>
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> > [Public]
> >
> >
> > Hi all,
> >
> >
> >
> > PFA, the patch that enables support for the next generation AMD Zen5 CPU 
> > via -
> march=znver5 with basic znver5 scheduler Model.
> >
> > We may update the scheduler model going forward.
> >
> >
> >
> > Good for trunk?
> >
> > Thanks and Regards
> > Karthiban
> >
> >
> > Patch is inline here.
> > From 6230938c1420604c8d0af27b0d080970d9b54ac5 Mon Sep 17 00:00:00
> 2001
> > From: karthiban
> karthiban.anbazha...@amd.com<mailto:karthiban.anbazha...@amd.com>
> > Date: Fri, 9 Feb 2024 15:03:09 +0530
> > Subject: [PATCH] Add AMD znver5 processor enablement with scheduler model
> >
> > gcc/ChangeLog:
> > * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver5.
> > * common/config/i386/i386-common.cc (processor_names): Add znver5.
> > (processor_alias_table): Likewise.
> > * common/config/i386/i386-cpuinfo.h (processor_types): Add new zen
> > family.
> > (processor_subtypes): Add znver5.
> > * config.gcc (x86_64-*-* |...): Likewise.
> > * config/i386/driver-i386.cc (host_detect_local_cpu): Let
> > march=native detect znver5 cpu's.
> > * config/i386/i386-c.cc (ix86_target_macros_internal): Add znver5.
> > * config/i386/i386-options.cc (m_ZNVER5): New definition
> > (processor_cost_table): Add znver5.
> > * config/i386/i386.cc (ix86_reassociation_width): Likewise.
> > * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER5
> > (PTA_ZNVER5): New definition.
> > * config/i386/i386.md (define_attr "cpu"): Add znver5.
> > (Scheduling descriptions) Add znver5.md.
> > * config/i386/x86-tune-costs.h (znver5_cost): New definition.
> > * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver5.
> > (ix86_adjust_cost): Likewise.
> > * config/i386/x86-tune.def (avx512_move_by_pieces): Add m_ZNVER5.
> > (avx512_store_by_pieces): Add m_ZNVER5.
> > * doc/extend.texi: Add znver5.
> > * doc/invoke.texi: Likewise.
> > * config/i386/znver5.md: New.
> >
> > gcc/testsuite/ChangeLog:
> > * g++.target/i386/mv29.C: Handle znver5 arch.
> > * gcc.target/i386/funcspec-56.inc:Likewise.
>
> Hi,
> I went through the scheduler description and found some places that can
> be commonized.  Most frequently it is the vector path instruction which
> blocks all execution cores so patterns can be shared between znver3 and
> 5 (blocking the new cores for znver3 does not change anything since they
> are not used anyway).  The insn automata growth is now about 5% which I
> hope is acceptable.  I tried the completely separate model and it was
> abour 7%.
>
> I plan to commit the patch tomorrow if htere are no further ideas for
> improvement.

Thank you for working on this.  The patch looks good.

Regards,
Venkat.

>
> Honza
>
> diff --git a/gcc/common/config/i386/cpuinfo.h
> b/gcc/common/config/i386/cpuinfo.h
> index a595ee537a8..017a952a5db 100644
> --- a/gcc/common/config/i386/cpuinfo.h
> +++ b/gcc/common/config/i386/cpuinfo.h
> @@ -310,6 +310,22 @@ get_amd_cpu (struct __processor_model *cpu_model,
>   cpu_model->__cpu_subtype = AMDFAM19H_ZNVER3;
> }
>break;
> +case 0x1a:
> +  cpu_model->__cpu_type = AMDFAM1AH;
> +  if (model <= 0x77)
> +   {
> + cpu = "znver5";
> + CHECK___builtin_cpu_is ("znver5");
> + cpu_model->__cpu_subtype = AMDFAM1AH_ZNVER5;
> +   }
> +  else if (has_cpu_feature (cpu_model, cpu_features2,
> +   FEATURE_AVX512VP2INTERSECT))
> +   {
> + cpu = "znver5";
> + CHECK___builtin_cpu_is ("znver5");
> + cpu_model->__cpu_subtype = AMDFAM1AH_ZNVER5;
> +   }
> +  break;
>  default:
>break;
>  }
> diff

Re: [PATCH] [X86_64]: Enable support for next generation AMD Zen5 CPU with znver5 scheduler Model

2024-03-11 Thread Jan Hubicka 
> [Public]
> 
> 
> Hi all,
> 
> 
> 
> PFA, the patch that enables support for the next generation AMD Zen5 CPU via 
> -march=znver5 with basic znver5 scheduler Model.
> 
> We may update the scheduler model going forward.
> 
> 
> 
> Good for trunk?
> 
> Thanks and Regards
> Karthiban
> 
> 
> Patch is inline here.
> From 6230938c1420604c8d0af27b0d080970d9b54ac5 Mon Sep 17 00:00:00 2001
> From: karthiban 
> karthiban.anbazha...@amd.com
> Date: Fri, 9 Feb 2024 15:03:09 +0530
> Subject: [PATCH] Add AMD znver5 processor enablement with scheduler model
> 
> gcc/ChangeLog:
> * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver5.
> * common/config/i386/i386-common.cc (processor_names): Add znver5.
> (processor_alias_table): Likewise.
> * common/config/i386/i386-cpuinfo.h (processor_types): Add new zen
> family.
> (processor_subtypes): Add znver5.
> * config.gcc (x86_64-*-* |...): Likewise.
> * config/i386/driver-i386.cc (host_detect_local_cpu): Let
> march=native detect znver5 cpu's.
> * config/i386/i386-c.cc (ix86_target_macros_internal): Add znver5.
> * config/i386/i386-options.cc (m_ZNVER5): New definition
> (processor_cost_table): Add znver5.
> * config/i386/i386.cc (ix86_reassociation_width): Likewise.
> * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER5
> (PTA_ZNVER5): New definition.
> * config/i386/i386.md (define_attr "cpu"): Add znver5.
> (Scheduling descriptions) Add znver5.md.
> * config/i386/x86-tune-costs.h (znver5_cost): New definition.
> * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver5.
> (ix86_adjust_cost): Likewise.
> * config/i386/x86-tune.def (avx512_move_by_pieces): Add m_ZNVER5.
> (avx512_store_by_pieces): Add m_ZNVER5.
> * doc/extend.texi: Add znver5.
> * doc/invoke.texi: Likewise.
> * config/i386/znver5.md: New.
> 
> gcc/testsuite/ChangeLog:
> * g++.target/i386/mv29.C: Handle znver5 arch.
> * gcc.target/i386/funcspec-56.inc:Likewise.

Hi,
I went through the scheduler description and found some places that can
be commonized.  Most frequently it is the vector path instruction which
blocks all execution cores so patterns can be shared between znver3 and
5 (blocking the new cores for znver3 does not change anything since they
are not used anyway).  The insn automata growth is now about 5% which I
hope is acceptable.  I tried the completely separate model and it was
abour 7%.

I plan to commit the patch tomorrow if htere are no further ideas for
improvement.

Honza

diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index a595ee537a8..017a952a5db 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -310,6 +310,22 @@ get_amd_cpu (struct __processor_model *cpu_model,
  cpu_model->__cpu_subtype = AMDFAM19H_ZNVER3;
}
   break;
+case 0x1a:
+  cpu_model->__cpu_type = AMDFAM1AH;
+  if (model <= 0x77)
+   {
+ cpu = "znver5";
+ CHECK___builtin_cpu_is ("znver5");
+ cpu_model->__cpu_subtype = AMDFAM1AH_ZNVER5;
+   }
+  else if (has_cpu_feature (cpu_model, cpu_features2,
+   FEATURE_AVX512VP2INTERSECT))
+   {
+ cpu = "znver5";
+ CHECK___builtin_cpu_is ("znver5");
+ cpu_model->__cpu_subtype = AMDFAM1AH_ZNVER5;
+   }
+  break;
 default:
   break;
 }
diff --git a/gcc/common/config/i386/i386-common.cc 
b/gcc/common/config/i386/i386-common.cc
index c35191e6925..f814df8385b 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -2166,7 +2166,8 @@ const char *const processor_names[] =
   "znver1",
   "znver2",
   "znver3",
-  "znver4"
+  "znver4",
+  "znver5"
 };
 
 /* Guarantee that the array is aligned with enum processor_type.  */
@@ -2435,6 +2436,9 @@ const pta processor_alias_table[] =
   {"znver4", PROCESSOR_ZNVER4, CPU_ZNVER4,
 PTA_ZNVER4,
 M_CPU_SUBTYPE (AMDFAM19H_ZNVER4), P_PROC_AVX512F},
+  {"znver5", PROCESSOR_ZNVER5, CPU_ZNVER5,
+PTA_ZNVER5,
+M_CPU_SUBTYPE (AMDFAM1AH_ZNVER5), P_PROC_AVX512F},
   {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
   | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_PRFCHW
diff --git a/gcc/common/config/i386/i386-cpuinfo.h 
b/gcc/common/config/i386/i386-cpuinfo.h
index 2ee7470c8da..73131657eab 100644
--- a/gcc/common/config/i386/i386-cpuinfo.h
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@@ -63,6 +63,7 @@ enum processor_types
   INTEL_SIERRAFOREST,
   INTEL_GRANDRIDGE,
   INTEL_CLEARWATERFOREST,
+  AMDFAM1AH,
   CPU_TYPE_MAX,
   BUILTIN_CPU_TYPE_MAX = CPU_TYPE_MAX
 };
@@ -104,6 +105,7 @@ enum processor_subtypes
   INTEL_COREI7_ARROWLAKE_S,
   INTEL_COREI7_PANTHERLAKE,

RE: [PATCH] [X86_64]: Enable support for next generation AMD Zen5 CPU with znver5 scheduler Model

2024-02-22 Thread Anbazhagan, Karthiban 
[Public]

Hi,

PFA, The patch that enables support for the next generation AMD Zen5 
CPU via -march=znver5 with basic znver5 scheduler Model.
znver5 scheduler model is combined with existing znver4 scheduler model 
into a single file "zn4zn5.md".

automata size tested using command :  size -A gcc/insn-automata.o
before patch: 1575958
After patch: 1670964

Thanks and Regards
Karthiban

-Original Message-
From: Anbazhagan, Karthiban
Sent: Wednesday, February 14, 2024 6:54 PM
To: Jan Hubicka 
Cc: gcc-patches@gcc.gnu.org; Kumar, Venkataramanan 
; Joshi, Tejas Sanjay 
; Nagarajan, Muthu kumar raj 
; Gopalasubramanian, Ganesh 

Subject: RE: [PATCH] [X86_64]: Enable support for next generation AMD Zen5 CPU 
with znver5 scheduler Model

Hi,

>>I assume the znver5 costs are smae as znver4 so far?

Costing table updated for below entries.
+  {COSTS_N_INSNS (10), /* cost of a divide/mod for QI.  */
+   COSTS_N_INSNS (11), /*  HI.  */
+   COSTS_N_INSNS (16), /*  DI.  */
+   COSTS_N_INSNS (16)},/*  
other.  */
+  COSTS_N_INSNS (10),  /* cost of DIVSS instruction.  
*/
+  COSTS_N_INSNS (14),  /* cost of SQRTSS instruction.  
*/
+  COSTS_N_INSNS (20),  /* cost of SQRTSD instruction.  
*/


>> we can just change znver4.md to also work for znver5?
We will combine znver4 and znver5 scheduler descriptions into one

Thanks and Regards
Karthiban

-Original Message-
From: Jan Hubicka 
Sent: Monday, February 12, 2024 9:30 PM
To: Anbazhagan, Karthiban 
Cc: gcc-patches@gcc.gnu.org; Kumar, Venkataramanan 
; Joshi, Tejas Sanjay 
; Nagarajan, Muthu kumar raj 
; Gopalasubramanian, Ganesh 

Subject: Re: [PATCH] [X86_64]: Enable support for next generation AMD Zen5 CPU 
with znver5 scheduler Model

Caution: This message originated from an External Source. Use proper caution 
when opening attachments, clicking links, or responding.


Hi,
> gcc/ChangeLog:
> * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver5.
> * common/config/i386/i386-common.cc (processor_names): Add znver5.
> (processor_alias_table): Likewise.
> * common/config/i386/i386-cpuinfo.h (processor_types): Add new zen
> family.
> (processor_subtypes): Add znver5.
> * config.gcc (x86_64-*-* |...): Likewise.
> * config/i386/driver-i386.cc (host_detect_local_cpu): Let
> march=native detect znver5 cpu's.
> * config/i386/i386-c.cc (ix86_target_macros_internal): Add znver5.
> * config/i386/i386-options.cc (m_ZNVER5): New definition
> (processor_cost_table): Add znver5.
> * config/i386/i386.cc (ix86_reassociation_width): Likewise.
> * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER5
> (PTA_ZNVER5): New definition.
> * config/i386/i386.md (define_attr "cpu"): Add znver5.
> (Scheduling descriptions) Add znver5.md.
> * config/i386/x86-tune-costs.h (znver5_cost): New definition.
> * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver5.
> (ix86_adjust_cost): Likewise.
> * config/i386/x86-tune.def (avx512_move_by_pieces): Add m_ZNVER5.
> (avx512_store_by_pieces): Add m_ZNVER5.
> * doc/extend.texi: Add znver5.
> * doc/invoke.texi: Likewise.
> * config/i386/znver5.md: New.
>
> gcc/testsuite/ChangeLog:
> * g++.target/i386/mv29.C: Handle znver5 arch.
> * gcc.target/i386/funcspec-56.inc:Likewise.
> +/* This table currently replicates znver4_cost table. */ struct
> +processor_costs znver5_cost = {

I assume the znver5 costs are smae as znver4 so far?

> +;; AMD znver5 Scheduling
> +;; Modeling automatons for zen decoders, integer execution pipes, ;;
> +AGU pipes, branch, floating point execution and fp store units.
> +(define_automaton "znver5, znver5_ieu, znver5_idiv, znver5_fdiv,
> +znver5_agu, znver5_fpu, znver5_fp_store")
> +
> +;; Decoders unit has 4 decoders and all of them can decode fast path
> +;; and vector type instructions.
> +(define_cpu_unit "znver5-decode0" "znver5") (define_cpu_unit
> +"znver5-decode1" "znver5") (define_cpu_unit "znver5-decode2"
> +"znver5") (define_cpu_unit "znver5-decode3" "znver5")

Duplicating znver4 description to znver5 before scheduler description is tuned 
is basically just leads to increasing compiler binary size (scheduler models 
are quite large).

Depending on changes between generations, I think we should try to share CPU 
unit DFAs where it makes sense (i.e.

Re: [PATCH] [X86_64]: Enable support for next generation AMD Zen5 CPU with znver5 scheduler Model

2024-02-14 Thread Jan Hubicka 
> [Public]
> 
> Hi,
> 
> >>I assume the znver5 costs are smae as znver4 so far?
> 
> Costing table updated for below entries.
> +  {COSTS_N_INSNS (10), /* cost of a divide/mod for QI.  */
> +   COSTS_N_INSNS (11), /*  HI.  */
> +   COSTS_N_INSNS (16), /*  DI.  */
> +   COSTS_N_INSNS (16)},/*  
> other.  */
> +  COSTS_N_INSNS (10),  /* cost of DIVSS instruction. 
>  */
> +  COSTS_N_INSNS (14),  /* cost of SQRTSS 
> instruction.  */
> +  COSTS_N_INSNS (20),  /* cost of SQRTSD 
> instruction.  */

I see, that looks good.
> 
> 
> >> we can just change znver4.md to also work for znver5?
> We will combine znver4 and znver5 scheduler descriptions into one

Thanks!

Honza
> 
> Thanks and Regards
> Karthiban
> 
> -Original Message-
> From: Jan Hubicka 
> Sent: Monday, February 12, 2024 9:30 PM
> To: Anbazhagan, Karthiban 
> Cc: gcc-patches@gcc.gnu.org; Kumar, Venkataramanan 
> ; Joshi, Tejas Sanjay 
> ; Nagarajan, Muthu kumar raj 
> ; Gopalasubramanian, Ganesh 
> 
> Subject: Re: [PATCH] [X86_64]: Enable support for next generation AMD Zen5 
> CPU with znver5 scheduler Model
> 
> Caution: This message originated from an External Source. Use proper caution 
> when opening attachments, clicking links, or responding.
> 
> 
> Hi,
> > gcc/ChangeLog:
> > * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver5.
> > * common/config/i386/i386-common.cc (processor_names): Add znver5.
> > (processor_alias_table): Likewise.
> > * common/config/i386/i386-cpuinfo.h (processor_types): Add new zen
> > family.
> > (processor_subtypes): Add znver5.
> > * config.gcc (x86_64-*-* |...): Likewise.
> > * config/i386/driver-i386.cc (host_detect_local_cpu): Let
> > march=native detect znver5 cpu's.
> > * config/i386/i386-c.cc (ix86_target_macros_internal): Add znver5.
> > * config/i386/i386-options.cc (m_ZNVER5): New definition
> > (processor_cost_table): Add znver5.
> > * config/i386/i386.cc (ix86_reassociation_width): Likewise.
> > * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER5
> > (PTA_ZNVER5): New definition.
> > * config/i386/i386.md (define_attr "cpu"): Add znver5.
> > (Scheduling descriptions) Add znver5.md.
> > * config/i386/x86-tune-costs.h (znver5_cost): New definition.
> > * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver5.
> > (ix86_adjust_cost): Likewise.
> > * config/i386/x86-tune.def (avx512_move_by_pieces): Add m_ZNVER5.
> > (avx512_store_by_pieces): Add m_ZNVER5.
> > * doc/extend.texi: Add znver5.
> > * doc/invoke.texi: Likewise.
> > * config/i386/znver5.md: New.
> >
> > gcc/testsuite/ChangeLog:
> > * g++.target/i386/mv29.C: Handle znver5 arch.
> > * gcc.target/i386/funcspec-56.inc:Likewise.
> > +/* This table currently replicates znver4_cost table. */ struct
> > +processor_costs znver5_cost = {
> 
> I assume the znver5 costs are smae as znver4 so far?
> 
> > +;; AMD znver5 Scheduling
> > +;; Modeling automatons for zen decoders, integer execution pipes, ;;
> > +AGU pipes, branch, floating point execution and fp store units.
> > +(define_automaton "znver5, znver5_ieu, znver5_idiv, znver5_fdiv,
> > +znver5_agu, znver5_fpu, znver5_fp_store")
> > +
> > +;; Decoders unit has 4 decoders and all of them can decode fast path
> > +;; and vector type instructions.
> > +(define_cpu_unit "znver5-decode0" "znver5") (define_cpu_unit
> > +"znver5-decode1" "znver5") (define_cpu_unit "znver5-decode2"
> > +"znver5") (define_cpu_unit "znver5-decode3" "znver5")
> 
> Duplicating znver4 description to znver5 before scheduler description is 
> tuned is basically just leads to increasing compiler binary size (scheduler 
> models are quite large).
> 
> Depending on changes between generations, I think we should try to share CPU 
> unit DFAs where it makes sense (i.e. shared DFA is smaller than two DFAs).  
> So perhaps unit scheduler is tuned, we can just change znver4.md to also work 
> for znver5?
> 
> Honza

RE: [PATCH] [X86_64]: Enable support for next generation AMD Zen5 CPU with znver5 scheduler Model

2024-02-14 Thread Anbazhagan, Karthiban 
[Public]

Hi,

>>I assume the znver5 costs are smae as znver4 so far?

Costing table updated for below entries.
+  {COSTS_N_INSNS (10), /* cost of a divide/mod for QI.  */
+   COSTS_N_INSNS (11), /*  HI.  */
+   COSTS_N_INSNS (16), /*  DI.  */
+   COSTS_N_INSNS (16)},/*  
other.  */
+  COSTS_N_INSNS (10),  /* cost of DIVSS instruction.  
*/
+  COSTS_N_INSNS (14),  /* cost of SQRTSS instruction.  
*/
+  COSTS_N_INSNS (20),  /* cost of SQRTSD instruction.  
*/


>> we can just change znver4.md to also work for znver5?
We will combine znver4 and znver5 scheduler descriptions into one

Thanks and Regards
Karthiban

-Original Message-
From: Jan Hubicka 
Sent: Monday, February 12, 2024 9:30 PM
To: Anbazhagan, Karthiban 
Cc: gcc-patches@gcc.gnu.org; Kumar, Venkataramanan 
; Joshi, Tejas Sanjay 
; Nagarajan, Muthu kumar raj 
; Gopalasubramanian, Ganesh 

Subject: Re: [PATCH] [X86_64]: Enable support for next generation AMD Zen5 CPU 
with znver5 scheduler Model

Caution: This message originated from an External Source. Use proper caution 
when opening attachments, clicking links, or responding.


Hi,
> gcc/ChangeLog:
> * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver5.
> * common/config/i386/i386-common.cc (processor_names): Add znver5.
> (processor_alias_table): Likewise.
> * common/config/i386/i386-cpuinfo.h (processor_types): Add new zen
> family.
> (processor_subtypes): Add znver5.
> * config.gcc (x86_64-*-* |...): Likewise.
> * config/i386/driver-i386.cc (host_detect_local_cpu): Let
> march=native detect znver5 cpu's.
> * config/i386/i386-c.cc (ix86_target_macros_internal): Add znver5.
> * config/i386/i386-options.cc (m_ZNVER5): New definition
> (processor_cost_table): Add znver5.
> * config/i386/i386.cc (ix86_reassociation_width): Likewise.
> * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER5
> (PTA_ZNVER5): New definition.
> * config/i386/i386.md (define_attr "cpu"): Add znver5.
> (Scheduling descriptions) Add znver5.md.
> * config/i386/x86-tune-costs.h (znver5_cost): New definition.
> * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver5.
> (ix86_adjust_cost): Likewise.
> * config/i386/x86-tune.def (avx512_move_by_pieces): Add m_ZNVER5.
> (avx512_store_by_pieces): Add m_ZNVER5.
> * doc/extend.texi: Add znver5.
> * doc/invoke.texi: Likewise.
> * config/i386/znver5.md: New.
>
> gcc/testsuite/ChangeLog:
> * g++.target/i386/mv29.C: Handle znver5 arch.
> * gcc.target/i386/funcspec-56.inc:Likewise.
> +/* This table currently replicates znver4_cost table. */ struct
> +processor_costs znver5_cost = {

I assume the znver5 costs are smae as znver4 so far?

> +;; AMD znver5 Scheduling
> +;; Modeling automatons for zen decoders, integer execution pipes, ;;
> +AGU pipes, branch, floating point execution and fp store units.
> +(define_automaton "znver5, znver5_ieu, znver5_idiv, znver5_fdiv,
> +znver5_agu, znver5_fpu, znver5_fp_store")
> +
> +;; Decoders unit has 4 decoders and all of them can decode fast path
> +;; and vector type instructions.
> +(define_cpu_unit "znver5-decode0" "znver5") (define_cpu_unit
> +"znver5-decode1" "znver5") (define_cpu_unit "znver5-decode2"
> +"znver5") (define_cpu_unit "znver5-decode3" "znver5")

Duplicating znver4 description to znver5 before scheduler description is tuned 
is basically just leads to increasing compiler binary size (scheduler models 
are quite large).

Depending on changes between generations, I think we should try to share CPU 
unit DFAs where it makes sense (i.e. shared DFA is smaller than two DFAs).  So 
perhaps unit scheduler is tuned, we can just change znver4.md to also work for 
znver5?

Honza

Re: [PATCH] [X86_64]: Enable support for next generation AMD Zen5 CPU with znver5 scheduler Model

2024-02-12 Thread Jan Hubicka 
Hi,
> gcc/ChangeLog:
> * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver5.
> * common/config/i386/i386-common.cc (processor_names): Add znver5.
> (processor_alias_table): Likewise.
> * common/config/i386/i386-cpuinfo.h (processor_types): Add new zen
> family.
> (processor_subtypes): Add znver5.
> * config.gcc (x86_64-*-* |...): Likewise.
> * config/i386/driver-i386.cc (host_detect_local_cpu): Let
> march=native detect znver5 cpu's.
> * config/i386/i386-c.cc (ix86_target_macros_internal): Add znver5.
> * config/i386/i386-options.cc (m_ZNVER5): New definition
> (processor_cost_table): Add znver5.
> * config/i386/i386.cc (ix86_reassociation_width): Likewise.
> * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER5
> (PTA_ZNVER5): New definition.
> * config/i386/i386.md (define_attr "cpu"): Add znver5.
> (Scheduling descriptions) Add znver5.md.
> * config/i386/x86-tune-costs.h (znver5_cost): New definition.
> * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver5.
> (ix86_adjust_cost): Likewise.
> * config/i386/x86-tune.def (avx512_move_by_pieces): Add m_ZNVER5.
> (avx512_store_by_pieces): Add m_ZNVER5.
> * doc/extend.texi: Add znver5.
> * doc/invoke.texi: Likewise.
> * config/i386/znver5.md: New.
> 
> gcc/testsuite/ChangeLog:
> * g++.target/i386/mv29.C: Handle znver5 arch.
> * gcc.target/i386/funcspec-56.inc:Likewise.
> +/* This table currently replicates znver4_cost table. */
> +struct processor_costs znver5_cost = {

I assume the znver5 costs are smae as znver4 so far?

> +;; AMD znver5 Scheduling
> +;; Modeling automatons for zen decoders, integer execution pipes,
> +;; AGU pipes, branch, floating point execution and fp store units.
> +(define_automaton "znver5, znver5_ieu, znver5_idiv, znver5_fdiv, znver5_agu, 
> znver5_fpu, znver5_fp_store")
> +
> +;; Decoders unit has 4 decoders and all of them can decode fast path
> +;; and vector type instructions.
> +(define_cpu_unit "znver5-decode0" "znver5")
> +(define_cpu_unit "znver5-decode1" "znver5")
> +(define_cpu_unit "znver5-decode2" "znver5")
> +(define_cpu_unit "znver5-decode3" "znver5")

Duplicating znver4 description to znver5 before scheduler description is
tuned is basically just leads to increasing compiler binary size
(scheduler models are quite large).

Depending on changes between generations, I think we should try to share
CPU unit DFAs where it makes sense (i.e. shared DFA is smaller than two
DFAs).  So perhaps unit scheduler is tuned, we can just change znver4.md
to also work for znver5?

Honza

Re: [PATCH] [X86_64]: Enable support for next generation AMD Zen5 CPU with znver5 scheduler Model

2024-02-11 Thread Richard Biener 
On Sat, Feb 10, 2024 at 1:55 PM Anbazhagan, Karthiban
 wrote:
>
> [Public]
>
>
> Hi all,
>
>
>
> PFA, the patch that enables support for the next generation AMD Zen5 CPU via 
> -march=znver5 with basic znver5 scheduler Model.
>
> We may update the scheduler model going forward.
>
>
>
> Good for trunk?

I'll note that gmail flagged this as spam, in case there's no response
from maintainers
I suggest to re-send.

The patch itself looks straight forward, I'll leave review to Honza/Uros though.

I'll note we have around eight processor_type left before eventually overflowing
the m_PROCESSOR mask ...

Thanks,
Richard.

> Thanks and Regards
>
> Karthiban
>
>
>
>
>
> Resending the patch, as unable to inline the patch here.
>
> reason : awaits moderator approval
>
> Message body is too big: 601858 bytes with a limit of 400 KB
>
>