Re: RE: [PATCH v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64

2023-06-18 Thread juzhe.zh...@rivai.ai 
I notice VWF_ZVE64 
should be removed.


juzhe.zh...@rivai.ai
 
From: Li, Pan2
Date: 2023-06-19 09:29
To: 钟居哲; gcc-patches
CC: rdapp.gcc; Jeff Law; Wang, Yanzhang; kito.cheng
Subject: RE: [PATCH v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64
Thanks Juzhe, will not send the V2 as only commit log change.
 
Pan
 
From: 钟居哲  
Sent: Monday, June 19, 2023 6:02 AM
To: Li, Pan2 ; gcc-patches 
Cc: rdapp.gcc ; Jeff Law ; Li, Pan2 
; Wang, Yanzhang ; kito.cheng 

Subject: Re: [PATCH v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64
 
Add target into changelog:
PR target/110299
 
Otherwise, LGTM.


juzhe.zh...@rivai.ai
 
From: pan2.li
Date: 2023-06-18 23:13
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64
From: Pan Li 
 
The rvv widdening reduction has 3 different patterns for zve128+, zve64
and zve32. They take the same iterator with different attributions.
However, we need the generated function code_for_reduc (code, mode1, mode2).
The implementation of code_for_reduc may look like below.
 
code_for_reduc (code, mode1, mode2)
{
  if (code == max && mode1 == VNx1HF && mode2 == VNx1HF)
return CODE_FOR_pred_reduc_maxvnx1hfvnx16hf; // ZVE128+
 
  if (code == max && mode1 == VNx1HF && mode2 == VNx1HF)
return CODE_FOR_pred_reduc_maxvnx1hfvnx8hf;  // ZVE64
 
  if (code == max && mode1 == VNx1HF && mode2 == VNx1HF)
return CODE_FOR_pred_reduc_maxvnx1hfvnx4hf;  // ZVE32
}
 
Thus there will be a problem here. For example zve32, we will have
code_for_reduc (max, VNx1HF, VNx1HF) which will return the code of
the ZVE128+ instead of the ZVE32 logically.
 
This patch will merge the 3 patterns into pattern, and pass both the
input_vector and the ret_vector of code_for_reduc. For example, ZVE32
will be code_for_reduc (max, VNx1HF, VNx2HF), then the correct code of ZVE32
will be returned as expectation.
 
Please note both GCC 13 and 14 are impacted by this issue.
 
Signed-off-by: Pan Li 
Co-Authored by: Juzhe-Zhong 
 
PR 110299
 
gcc/ChangeLog:
 
* config/riscv/riscv-vector-builtins-bases.cc: Adjust expand for
modes.
* config/riscv/vector-iterators.md: Remove VWLMUL1, VWLMUL1_ZVE64,
VWLMUL1_ZVE32.
* config/riscv/vector.md
(@pred_widen_reduc_plus): Removed.
(@pred_widen_reduc_plus): Ditto.
(@pred_widen_reduc_plus): Ditto.
(@pred_widen_reduc_plus): Ditto.
(@pred_widen_reduc_plus): Ditto.
(@pred_widen_reduc_plus): New pattern.
(@pred_widen_reduc_plus): Ditto.
(@pred_widen_reduc_plus): Ditto.
(@pred_widen_reduc_plus): Ditto.
(@pred_widen_reduc_plus): Ditto.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/base/pr110299-1.c: New test.
* gcc.target/riscv/rvv/base/pr110299-1.h: New test.
* gcc.target/riscv/rvv/base/pr110299-2.c: New test.
* gcc.target/riscv/rvv/base/pr110299-2.h: New test.
* gcc.target/riscv/rvv/base/pr110299-3.c: New test.
* gcc.target/riscv/rvv/base/pr110299-3.h: New test.
* gcc.target/riscv/rvv/base/pr110299-4.c: New test.
* gcc.target/riscv/rvv/base/pr110299-4.h: New test.
---
.../riscv/riscv-vector-builtins-bases.cc  |  16 +-
gcc/config/riscv/vector-iterators.md  |  62 -
gcc/config/riscv/vector.md| 243 --
.../gcc.target/riscv/rvv/base/pr110299-1.c|   7 +
.../gcc.target/riscv/rvv/base/pr110299-1.h|   9 +
.../gcc.target/riscv/rvv/base/pr110299-2.c|   8 +
.../gcc.target/riscv/rvv/base/pr110299-2.h|  17 ++
.../gcc.target/riscv/rvv/base/pr110299-3.c|   7 +
.../gcc.target/riscv/rvv/base/pr110299-3.h|  17 ++
.../gcc.target/riscv/rvv/base/pr110299-4.c|   8 +
.../gcc.target/riscv/rvv/base/pr110299-4.h|  17 ++
11 files changed, 253 insertions(+), 158 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.h
 
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 27545113996..c6c53dc13a5 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1396,16 +1396,8 @@ public:
   rtx expand (function_expander ) const override
   {
-machine_mode mode = e.vector_mode ();
-machine_mode ret_mode = e.ret_mode ();
-
-/* TODO: we will use ret_mode after all types of PR110265 are addressed.  
*/
-if (GET_MODE_INNER (mode) != GET_MODE_INNER (ret_mode))
-  return e.use_exact_insn (
- code_for_p

RE: [PATCH v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64

2023-06-18 Thread Li, Pan2 via Gcc-patches 
Thanks Juzhe, will not send the V2 as only commit log change.

Pan

From: 钟居哲 
Sent: Monday, June 19, 2023 6:02 AM
To: Li, Pan2 ; gcc-patches 
Cc: rdapp.gcc ; Jeff Law ; Li, Pan2 
; Wang, Yanzhang ; kito.cheng 

Subject: Re: [PATCH v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64

Add target into changelog:
PR target/110299

Otherwise, LGTM.

juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>

From: pan2.li<mailto:pan2...@intel.com>
Date: 2023-06-18 23:13
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>; 
rdapp.gcc<mailto:rdapp@gmail.com>; 
jeffreyalaw<mailto:jeffreya...@gmail.com>; pan2.li<mailto:pan2...@intel.com>; 
yanzhang.wang<mailto:yanzhang.w...@intel.com>; 
kito.cheng<mailto:kito.ch...@gmail.com>
Subject: [PATCH v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64
From: Pan Li mailto:pan2...@intel.com>>

The rvv widdening reduction has 3 different patterns for zve128+, zve64
and zve32. They take the same iterator with different attributions.
However, we need the generated function code_for_reduc (code, mode1, mode2).
The implementation of code_for_reduc may look like below.

code_for_reduc (code, mode1, mode2)
{
  if (code == max && mode1 == VNx1HF && mode2 == VNx1HF)
return CODE_FOR_pred_reduc_maxvnx1hfvnx16hf; // ZVE128+

  if (code == max && mode1 == VNx1HF && mode2 == VNx1HF)
return CODE_FOR_pred_reduc_maxvnx1hfvnx8hf;  // ZVE64

  if (code == max && mode1 == VNx1HF && mode2 == VNx1HF)
return CODE_FOR_pred_reduc_maxvnx1hfvnx4hf;  // ZVE32
}

Thus there will be a problem here. For example zve32, we will have
code_for_reduc (max, VNx1HF, VNx1HF) which will return the code of
the ZVE128+ instead of the ZVE32 logically.

This patch will merge the 3 patterns into pattern, and pass both the
input_vector and the ret_vector of code_for_reduc. For example, ZVE32
will be code_for_reduc (max, VNx1HF, VNx2HF), then the correct code of ZVE32
will be returned as expectation.

Please note both GCC 13 and 14 are impacted by this issue.

Signed-off-by: Pan Li mailto:pan2...@intel.com>>
Co-Authored by: Juzhe-Zhong mailto:juzhe.zh...@rivai.ai>>

PR 110299

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-bases.cc: Adjust expand for
modes.
* config/riscv/vector-iterators.md: Remove VWLMUL1, VWLMUL1_ZVE64,
VWLMUL1_ZVE32.
* config/riscv/vector.md
(@pred_widen_reduc_plus): Removed.
(@pred_widen_reduc_plus): Ditto.
(@pred_widen_reduc_plus): Ditto.
(@pred_widen_reduc_plus): Ditto.
(@pred_widen_reduc_plus): Ditto.
(@pred_widen_reduc_plus): New pattern.
(@pred_widen_reduc_plus): Ditto.
(@pred_widen_reduc_plus): Ditto.
(@pred_widen_reduc_plus): Ditto.
(@pred_widen_reduc_plus): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pr110299-1.c: New test.
* gcc.target/riscv/rvv/base/pr110299-1.h: New test.
* gcc.target/riscv/rvv/base/pr110299-2.c: New test.
* gcc.target/riscv/rvv/base/pr110299-2.h: New test.
* gcc.target/riscv/rvv/base/pr110299-3.c: New test.
* gcc.target/riscv/rvv/base/pr110299-3.h: New test.
* gcc.target/riscv/rvv/base/pr110299-4.c: New test.
* gcc.target/riscv/rvv/base/pr110299-4.h: New test.
---
.../riscv/riscv-vector-builtins-bases.cc  |  16 +-
gcc/config/riscv/vector-iterators.md  |  62 -
gcc/config/riscv/vector.md| 243 --
.../gcc.target/riscv/rvv/base/pr110299-1.c|   7 +
.../gcc.target/riscv/rvv/base/pr110299-1.h|   9 +
.../gcc.target/riscv/rvv/base/pr110299-2.c|   8 +
.../gcc.target/riscv/rvv/base/pr110299-2.h|  17 ++
.../gcc.target/riscv/rvv/base/pr110299-3.c|   7 +
.../gcc.target/riscv/rvv/base/pr110299-3.h|  17 ++
.../gcc.target/riscv/rvv/base/pr110299-4.c|   8 +
.../gcc.target/riscv/rvv/base/pr110299-4.h|  17 ++
11 files changed, 253 insertions(+), 158 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.h

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 27545113996..c6c53dc13a5 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1396,16 +1396,8 @@ public:
   rtx expand (function_expander ) const override
   {
-machine_mode mode = e.vector_mode ();
-machine_mode ret_mode = e.ret_mode ();
-
-/* TODO: we will

Re: [PATCH v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64

2023-06-18 Thread 钟居哲 
Add target into changelog:
PR target/110299

Otherwise, LGTM.


juzhe.zh...@rivai.ai
 
From: pan2.li
Date: 2023-06-18 23:13
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64
From: Pan Li 
 
The rvv widdening reduction has 3 different patterns for zve128+, zve64
and zve32. They take the same iterator with different attributions.
However, we need the generated function code_for_reduc (code, mode1, mode2).
The implementation of code_for_reduc may look like below.
 
code_for_reduc (code, mode1, mode2)
{
  if (code == max && mode1 == VNx1HF && mode2 == VNx1HF)
return CODE_FOR_pred_reduc_maxvnx1hfvnx16hf; // ZVE128+
 
  if (code == max && mode1 == VNx1HF && mode2 == VNx1HF)
return CODE_FOR_pred_reduc_maxvnx1hfvnx8hf;  // ZVE64
 
  if (code == max && mode1 == VNx1HF && mode2 == VNx1HF)
return CODE_FOR_pred_reduc_maxvnx1hfvnx4hf;  // ZVE32
}
 
Thus there will be a problem here. For example zve32, we will have
code_for_reduc (max, VNx1HF, VNx1HF) which will return the code of
the ZVE128+ instead of the ZVE32 logically.
 
This patch will merge the 3 patterns into pattern, and pass both the
input_vector and the ret_vector of code_for_reduc. For example, ZVE32
will be code_for_reduc (max, VNx1HF, VNx2HF), then the correct code of ZVE32
will be returned as expectation.
 
Please note both GCC 13 and 14 are impacted by this issue.
 
Signed-off-by: Pan Li 
Co-Authored by: Juzhe-Zhong 
 
PR 110299
 
gcc/ChangeLog:
 
* config/riscv/riscv-vector-builtins-bases.cc: Adjust expand for
modes.
* config/riscv/vector-iterators.md: Remove VWLMUL1, VWLMUL1_ZVE64,
VWLMUL1_ZVE32.
* config/riscv/vector.md
(@pred_widen_reduc_plus): Removed.
(@pred_widen_reduc_plus): Ditto.
(@pred_widen_reduc_plus): Ditto.
(@pred_widen_reduc_plus): Ditto.
(@pred_widen_reduc_plus): Ditto.
(@pred_widen_reduc_plus): New pattern.
(@pred_widen_reduc_plus): Ditto.
(@pred_widen_reduc_plus): Ditto.
(@pred_widen_reduc_plus): Ditto.
(@pred_widen_reduc_plus): Ditto.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/base/pr110299-1.c: New test.
* gcc.target/riscv/rvv/base/pr110299-1.h: New test.
* gcc.target/riscv/rvv/base/pr110299-2.c: New test.
* gcc.target/riscv/rvv/base/pr110299-2.h: New test.
* gcc.target/riscv/rvv/base/pr110299-3.c: New test.
* gcc.target/riscv/rvv/base/pr110299-3.h: New test.
* gcc.target/riscv/rvv/base/pr110299-4.c: New test.
* gcc.target/riscv/rvv/base/pr110299-4.h: New test.
---
.../riscv/riscv-vector-builtins-bases.cc  |  16 +-
gcc/config/riscv/vector-iterators.md  |  62 -
gcc/config/riscv/vector.md| 243 --
.../gcc.target/riscv/rvv/base/pr110299-1.c|   7 +
.../gcc.target/riscv/rvv/base/pr110299-1.h|   9 +
.../gcc.target/riscv/rvv/base/pr110299-2.c|   8 +
.../gcc.target/riscv/rvv/base/pr110299-2.h|  17 ++
.../gcc.target/riscv/rvv/base/pr110299-3.c|   7 +
.../gcc.target/riscv/rvv/base/pr110299-3.h|  17 ++
.../gcc.target/riscv/rvv/base/pr110299-4.c|   8 +
.../gcc.target/riscv/rvv/base/pr110299-4.h|  17 ++
11 files changed, 253 insertions(+), 158 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.h
 
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 27545113996..c6c53dc13a5 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1396,16 +1396,8 @@ public:
   rtx expand (function_expander ) const override
   {
-machine_mode mode = e.vector_mode ();
-machine_mode ret_mode = e.ret_mode ();
-
-/* TODO: we will use ret_mode after all types of PR110265 are addressed.  
*/
-if (GET_MODE_INNER (mode) != GET_MODE_INNER (ret_mode))
-  return e.use_exact_insn (
- code_for_pred_reduc (CODE, e.vector_mode (), e.vector_mode ()));
-else
-  return e.use_exact_insn (
- code_for_pred_reduc (CODE, e.vector_mode (), e.ret_mode ()));
+return e.use_exact_insn (
+  code_for_pred_reduc (CODE, e.vector_mode (), e.ret_mode ()));
   }
};
@@ -1420,7 +1412,7 @@ public:
   {
 return e.use_exact_insn (code_for_pred_widen_reduc_plus (UNSPEC,
 e.vector_mode (),
-  e.vector_mode ()));
+  e.ret_mode ()));
   }
};
@@ -1449,7 +1441,7 @@ public:
   {
 return e.use_exact_insn (code_for_pred_widen_reduc_plus (UNSPEC,
 e.vector_mode (),
-  e.vector_mode