Hi Srinath, > -----Original Message----- > From: Srinath Parvathaneni <srinath.parvathan...@arm.com> > Sent: 16 March 2020 12:01 > To: gcc-patches@gcc.gnu.org > Cc: Kyrylo Tkachov <kyrylo.tkac...@arm.com> > Subject: [PATCH v2][ARM][GCC][1/3x]: MVE intrinsics with ternary operands. > > Hello Kyrill, > > Following patch is the rebased version of v1. > (version v1) https://gcc.gnu.org/pipermail/gcc-patches/2019- > November/534358.html > > #### > > Hello, > > This patch supports following MVE ACLE intrinsics with ternary operands. > > vabavq_s8, vabavq_s16, vabavq_s32, vbicq_m_n_s16, vbicq_m_n_s32, > vbicq_m_n_u16, vbicq_m_n_u32, vcmpeqq_m_f16, vcmpeqq_m_f32, > vcvtaq_m_s16_f16, vcvtaq_m_u16_f16, vcvtaq_m_s32_f32, > vcvtaq_m_u32_f32, vcvtq_m_f16_s16, vcvtq_m_f16_u16, vcvtq_m_f32_s32, > vcvtq_m_f32_u32, vqrshrnbq_n_s16, vqrshrnbq_n_u16, vqrshrnbq_n_s32, > vqrshrnbq_n_u32, vqrshrunbq_n_s16, vqrshrunbq_n_s32, > vrmlaldavhaq_s32, vrmlaldavhaq_u32, vshlcq_s8, vshlcq_u8, vshlcq_s16, > vshlcq_u16, vshlcq_s32, vshlcq_u32, vabavq_s8, vabavq_s16, vabavq_s32. > > Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more > details. > [1] https://developer.arm.com/architectures/instruction-sets/simd- > isas/helium/mve-intrinsics > > Regression tested on arm-none-eabi and found no regressions. > > Ok for trunk?
I've pushed this patch to master for you. Thanks, Kyrill > > Thanks, > Srinath. > > gcc/ChangeLog: > > 2019-10-23 Andre Vieira <andre.simoesdiasvie...@arm.com> > Mihail Ionescu <mihail.ione...@arm.com> > Srinath Parvathaneni <srinath.parvathan...@arm.com> > > * config/arm/arm-builtins.c > (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): > Define qualifier for ternary operands. > (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise. > (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. > (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. > (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise. > (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. > (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. > (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. > (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise. > (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. > (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. > (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise. > (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. > (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise. > * config/arm/arm_mve.h (vabavq_s8): Define macro. > (vabavq_s16): Likewise. > (vabavq_s32): Likewise. > (vbicq_m_n_s16): Likewise. > (vbicq_m_n_s32): Likewise. > (vbicq_m_n_u16): Likewise. > (vbicq_m_n_u32): Likewise. > (vcmpeqq_m_f16): Likewise. > (vcmpeqq_m_f32): Likewise. > (vcvtaq_m_s16_f16): Likewise. > (vcvtaq_m_u16_f16): Likewise. > (vcvtaq_m_s32_f32): Likewise. > (vcvtaq_m_u32_f32): Likewise. > (vcvtq_m_f16_s16): Likewise. > (vcvtq_m_f16_u16): Likewise. > (vcvtq_m_f32_s32): Likewise. > (vcvtq_m_f32_u32): Likewise. > (vqrshrnbq_n_s16): Likewise. > (vqrshrnbq_n_u16): Likewise. > (vqrshrnbq_n_s32): Likewise. > (vqrshrnbq_n_u32): Likewise. > (vqrshrunbq_n_s16): Likewise. > (vqrshrunbq_n_s32): Likewise. > (vrmlaldavhaq_s32): Likewise. > (vrmlaldavhaq_u32): Likewise. > (vshlcq_s8): Likewise. > (vshlcq_u8): Likewise. > (vshlcq_s16): Likewise. > (vshlcq_u16): Likewise. > (vshlcq_s32): Likewise. > (vshlcq_u32): Likewise. > (vabavq_u8): Likewise. > (vabavq_u16): Likewise. > (vabavq_u32): Likewise. > (__arm_vabavq_s8): Define intrinsic. > (__arm_vabavq_s16): Likewise. > (__arm_vabavq_s32): Likewise. > (__arm_vabavq_u8): Likewise. > (__arm_vabavq_u16): Likewise. > (__arm_vabavq_u32): Likewise. > (__arm_vbicq_m_n_s16): Likewise. > (__arm_vbicq_m_n_s32): Likewise. > (__arm_vbicq_m_n_u16): Likewise. > (__arm_vbicq_m_n_u32): Likewise. > (__arm_vqrshrnbq_n_s16): Likewise. > (__arm_vqrshrnbq_n_u16): Likewise. > (__arm_vqrshrnbq_n_s32): Likewise. > (__arm_vqrshrnbq_n_u32): Likewise. > (__arm_vqrshrunbq_n_s16): Likewise. > (__arm_vqrshrunbq_n_s32): Likewise. > (__arm_vrmlaldavhaq_s32): Likewise. > (__arm_vrmlaldavhaq_u32): Likewise. > (__arm_vshlcq_s8): Likewise. > (__arm_vshlcq_u8): Likewise. > (__arm_vshlcq_s16): Likewise. > (__arm_vshlcq_u16): Likewise. > (__arm_vshlcq_s32): Likewise. > (__arm_vshlcq_u32): Likewise. > (__arm_vcmpeqq_m_f16): Likewise. > (__arm_vcmpeqq_m_f32): Likewise. > (__arm_vcvtaq_m_s16_f16): Likewise. > (__arm_vcvtaq_m_u16_f16): Likewise. > (__arm_vcvtaq_m_s32_f32): Likewise. > (__arm_vcvtaq_m_u32_f32): Likewise. > (__arm_vcvtq_m_f16_s16): Likewise. > (__arm_vcvtq_m_f16_u16): Likewise. > (__arm_vcvtq_m_f32_s32): Likewise. > (__arm_vcvtq_m_f32_u32): Likewise. > (vcvtaq_m): Define polymorphic variant. > (vcvtq_m): Likewise. > (vabavq): Likewise. > (vshlcq): Likewise. > (vbicq_m_n): Likewise. > (vqrshrnbq_n): Likewise. > (vqrshrunbq_n): Likewise. > * config/arm/arm_mve_builtins.def > (TERNOP_UNONE_UNONE_UNONE_IMM_QUALIFIERS): Use the > builtin qualifer. > (TERNOP_UNONE_UNONE_NONE_NONE_QUALIFIERS): Likewise. > (TERNOP_UNONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. > (TERNOP_NONE_NONE_UNONE_IMM_QUALIFIERS): Likewise. > (TERNOP_UNONE_UNONE_NONE_IMM_QUALIFIERS): Likewise. > (TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Likewise. > (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Likewise. > (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. > (TERNOP_NONE_NONE_NONE_IMM_QUALIFIERS): Likewise. > (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Likewise. > (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Likewise. > (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Likewise. > (TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Likewise. > (TERNOP_NONE_NONE_NONE_NONE_QUALIFIERS): Likewise. > * config/arm/mve.md (VBICQ_M_N): Define iterator. > (VCVTAQ_M): Likewise. > (VCVTQ_M_TO_F): Likewise. > (VQRSHRNBQ_N): Likewise. > (VABAVQ): Likewise. > (VSHLCQ): Likewise. > (VRMLALDAVHAQ): Likewise. > (mve_vbicq_m_n_<supf><mode>): Define RTL pattern. > (mve_vcmpeqq_m_f<mode>): Likewise. > (mve_vcvtaq_m_<supf><mode>): Likewise. > (mve_vcvtq_m_to_f_<supf><mode>): Likewise. > (mve_vqrshrnbq_n_<supf><mode>): Likewise. > (mve_vqrshrunbq_n_s<mode>): Likewise. > (mve_vrmlaldavhaq_<supf>v4si): Likewise. > (mve_vabavq_<supf><mode>): Likewise. > (mve_vshlcq_<supf><mode>): Likewise. > (mve_vshlcq_<supf><mode>): Likewise. > (mve_vshlcq_vec_<supf><mode>): Define RTL expand. > (mve_vshlcq_carry_<supf><mode>): Likewise. > > gcc/testsuite/ChangeLog: > > 2019-10-23 Andre Vieira <andre.simoesdiasvie...@arm.com> > Mihail Ionescu <mihail.ione...@arm.com> > Srinath Parvathaneni <srinath.parvathan...@arm.com> > > * gcc.target/arm/mve/intrinsics/vabavq_s16.c: New test. > * gcc.target/arm/mve/intrinsics/vabavq_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vabavq_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vabavq_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vabavq_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vabavq_u8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcvtaq_m_s32_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcvtaq_m_u16_f16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcvtaq_m_u32_f32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vqrshrunbq_n_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vshlcq_s16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vshlcq_s32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vshlcq_s8.c: Likewise. > * gcc.target/arm/mve/intrinsics/vshlcq_u16.c: Likewise. > * gcc.target/arm/mve/intrinsics/vshlcq_u32.c: Likewise. > * gcc.target/arm/mve/intrinsics/vshlcq_u8.c: Likewise.
