Re: RISCV: Add zmmul extension

[Jim Wilson]

On Wed, Oct 27, 2021 at 12:14 AM Kito Cheng  wrote:

> Otherwise it is LGTM, but I'm just surprised it's still 0.1 and not frozen
> yet.
>

We should have binutils support first before we have gcc support.
Otherwise that may lead to binutils errors later when zmmul gets passed
down to binutils.  I didn't see a binutils patch yet.

Jim

Re: RISCV: Add zmmul extension

[Kito Cheng]

Hi Shi-Hua:

> --- a/gcc/config/riscv/riscv.c
> +++ b/gcc/config/riscv/riscv.c
> @@ -1872,7 +1872,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int 
> outer_code, int opno ATTRIBUTE_UN
>  case MULT:
>if (float_mode_p)
> *total = tune_param->fp_mul[mode == DFmode];
> -  else if (!TARGET_MUL)
> +  else if (!TARGET_MUL && !TARGET_ZMMUL)
> /* Estimate the cost of a library call.  */
> *total = COSTS_N_INSNS (speed ? 32 : 6);
>else if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
> @@ -4736,6 +4736,9 @@ riscv_option_override (void)
>if (flag_pic)
>  g_switch_value = 0;
>
> +  /* zmmul */
> +  if (TARGET_ZMMUL && TARGET_MUL)
> +error ("can not use both the % and the % extension");

My understanding is zmmul and M are not mutually exclusive, so we
don't need this check,

Otherwise it is LGTM, but I'm just surprised it's still 0.1 and not frozen yet.

[1] https://github.com/riscv/riscv-isa-manual/pull/648#issuecomment-842461775

RISCV: Add zmmul extension

[shihua]

From: Liaoshihua 

---
 gcc/common/config/riscv/riscv-common.c |  3 +++
 gcc/config/riscv/riscv-c.c |  2 +-
 gcc/config/riscv/riscv-opts.h  |  3 +++
 gcc/config/riscv/riscv.c   |  5 -
 gcc/config/riscv/riscv.md  | 30 +-
 gcc/config/riscv/riscv.opt |  3 +++
 6 files changed, 29 insertions(+), 17 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.c 
b/gcc/common/config/riscv/riscv-common.c
index 34b74e52a2d..ad3180677be 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -101,6 +101,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
   {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
 
+  {"zmmul",  ISA_SPEC_CLASS_NONE, 0, 1},
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -904,6 +905,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"zicsr",_options::x_riscv_zi_subext, MASK_ZICSR},
   {"zifencei", _options::x_riscv_zi_subext, MASK_ZIFENCEI},
 
+  {"zmmul", _options::x_riscv_zmmul_subext, MASK_ZMMUL},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv-c.c b/gcc/config/riscv/riscv-c.c
index efd4a61ea29..72aa4e389c0 100644
--- a/gcc/config/riscv/riscv-c.c
+++ b/gcc/config/riscv/riscv-c.c
@@ -47,7 +47,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
   if (TARGET_ATOMIC)
 builtin_define ("__riscv_atomic");
 
-  if (TARGET_MUL)
+  if (TARGET_MUL || TARGET_ZMMUL)
 builtin_define ("__riscv_mul");
   if (TARGET_DIV)
 builtin_define ("__riscv_div");
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index f4cf6ca4b82..c52b18ebd80 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -73,4 +73,7 @@ enum stack_protector_guard {
 #define TARGET_ZICSR((riscv_zi_subext & MASK_ZICSR) != 0)
 #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
 
+#define MASK_ZMMUL (1 << 0)
+#define TARGET_ZMMUL ((riscv_zmmul_subext & MASK_ZMMUL) != 0)
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 17cdf705c32..4f5cb35e625 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -1872,7 +1872,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int 
outer_code, int opno ATTRIBUTE_UN
 case MULT:
   if (float_mode_p)
*total = tune_param->fp_mul[mode == DFmode];
-  else if (!TARGET_MUL)
+  else if (!TARGET_MUL && !TARGET_ZMMUL)
/* Estimate the cost of a library call.  */
*total = COSTS_N_INSNS (speed ? 32 : 6);
   else if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
@@ -4736,6 +4736,9 @@ riscv_option_override (void)
   if (flag_pic)
 g_switch_value = 0;
 
+  /* zmmul */
+  if (TARGET_ZMMUL && TARGET_MUL)
+error ("can not use both the % and the % extension");
   /* The presence of the M extension implies that division instructions
  are present, so include them unless explicitly disabled.  */
   if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index c3687d57047..2ee7d801f1a 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -600,7 +600,7 @@
   [(set (match_operand:SI  0 "register_operand" "=r")
(mult:SI (match_operand:SI 1 "register_operand" " r")
 (match_operand:SI 2 "register_operand" " r")))]
-  "TARGET_MUL"
+  "(TARGET_MUL || TARGET_ZMMUL)"
   { return TARGET_64BIT ? "mulw\t%0,%1,%2" : "mul\t%0,%1,%2"; }
   [(set_attr "type" "imul")
(set_attr "mode" "SI")])
@@ -609,7 +609,7 @@
   [(set (match_operand:DI  0 "register_operand" "=r")
(mult:DI (match_operand:DI 1 "register_operand" " r")
 (match_operand:DI 2 "register_operand" " r")))]
-  "TARGET_MUL && TARGET_64BIT"
+  "(TARGET_MUL || TARGET_ZMMUL) && TARGET_64BIT"
   "mul\t%0,%1,%2"
   [(set_attr "type" "imul")
(set_attr "mode" "DI")])
@@ -619,7 +619,7 @@
(sign_extend:DI
(mult:SI (match_operand:SI 1 "register_operand" " r")
 (match_operand:SI 2 "register_operand" " r"]
-  "TARGET_MUL && TARGET_64BIT"
+  "(TARGET_MUL || TARGET_ZMMUL) && TARGET_64BIT"
   "mulw\t%0,%1,%2"
   [(set_attr "type" "imul")
(set_attr "mode" "SI")])
@@ -630,7 +630,7 @@
  (match_operator:SI 3 "subreg_lowpart_operator"
[(mult:DI (match_operand:DI 1 "register_operand" " r")
  (match_operand:DI 2 "register_operand" " r"))])))]
-  "TARGET_MUL && TARGET_64BIT"
+  "(TARGET_MUL || TARGET_ZMMUL) && TARGET_64BIT"
   "mulw\t%0,%1,%2"
   [(set_attr "type" "imul")
(set_attr "mode" "SI")])
@@ -648,7 +648,7 @@
   [(set (match_operand:TI 0 "register_operand")
(mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
 (any_extend:TI (match_operand:DI 2