For machines that satisfy ISA_HAS_LSX && !TARGET_64BIT, we will not support
them now
and in the future, so this patch removes these unused code.
gcc/ChangeLog:
* config/loongarch/lasx.md: Remove unused code.
* config/loongarch/loongarch-protos.h (loongarch_split_lsx_copy_d):
Remove.
(loongarch_split_lsx_insert_d): Ditto.
(loongarch_split_lsx_fill_d): Ditto.
* config/loongarch/loongarch.cc (loongarch_split_lsx_copy_d): Ditto.
(loongarch_split_lsx_insert_d): Ditto.
(loongarch_split_lsx_fill_d): Ditto.
* config/loongarch/lsx.md (lsx_vpickve2gr_du): Remove splitter.
(lsx_vpickve2gr_<lsxfmt_f>): Ditto.
(abs<mode>2): Remove expander.
(vabs<mode>2): Rename to abs<mode>2.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/vector/lsx/lsx-abs.c: New test.
---
gcc/config/loongarch/lasx.md | 12 +--
gcc/config/loongarch/loongarch-protos.h | 3 -
gcc/config/loongarch/loongarch.cc | 76 ----------------
gcc/config/loongarch/lsx.md | 89 ++-----------------
.../gcc.target/loongarch/vector/lsx/lsx-abs.c | 26 ++++++
5 files changed, 35 insertions(+), 171 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-abs.c
diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index 2fa5e46c8e8..7bd61f8ed5b 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -572,12 +572,7 @@ (define_insn "lasx_xvinsgr2vr_<lasxfmt_f_wd>"
(match_operand 3 "const_<bitmask256>_operand" "")))]
"ISA_HAS_LASX"
{
-#if 0
- if (!TARGET_64BIT && (<MODE>mode == V4DImode || <MODE>mode == V4DFmode))
- return "#";
- else
-#endif
- return "xvinsgr2vr.<lasxfmt>\t%u0,%z1,%y3";
+ return "xvinsgr2vr.<lasxfmt>\t%u0,%z1,%y3";
}
[(set_attr "type" "simd_insert")
(set_attr "mode" "<MODE>")])
@@ -1446,10 +1441,7 @@ (define_insn "lasx_xvreplgr2vr_<lasxfmt_f>"
if (which_alternative == 1)
return "xvldi.b\t%u0,0" ;
- if (!TARGET_64BIT && (<MODE>mode == V2DImode || <MODE>mode == V2DFmode))
- return "#";
- else
- return "xvreplgr2vr.<lasxfmt>\t%u0,%z1";
+ return "xvreplgr2vr.<lasxfmt>\t%u0,%z1";
}
[(set_attr "type" "simd_fill")
(set_attr "mode" "<MODE>")
diff --git a/gcc/config/loongarch/loongarch-protos.h
b/gcc/config/loongarch/loongarch-protos.h
index e3ed2b912a5..e238d795a73 100644
--- a/gcc/config/loongarch/loongarch-protos.h
+++ b/gcc/config/loongarch/loongarch-protos.h
@@ -89,9 +89,6 @@ extern void loongarch_split_128bit_move (rtx, rtx);
extern bool loongarch_split_128bit_move_p (rtx, rtx);
extern void loongarch_split_256bit_move (rtx, rtx);
extern bool loongarch_split_256bit_move_p (rtx, rtx);
-extern void loongarch_split_lsx_copy_d (rtx, rtx, rtx, rtx (*)(rtx, rtx, rtx));
-extern void loongarch_split_lsx_insert_d (rtx, rtx, rtx, rtx);
-extern void loongarch_split_lsx_fill_d (rtx, rtx);
extern const char *loongarch_output_move (rtx, rtx);
#ifdef RTX_CODE
extern void loongarch_expand_scc (rtx *);
diff --git a/gcc/config/loongarch/loongarch.cc
b/gcc/config/loongarch/loongarch.cc
index a69a203fbe6..8438cc64b0d 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -4756,82 +4756,6 @@ loongarch_split_256bit_move (rtx dest, rtx src)
}
}
-
-/* Split a COPY_S.D with operands DEST, SRC and INDEX. GEN is a function
- used to generate subregs. */
-
-void
-loongarch_split_lsx_copy_d (rtx dest, rtx src, rtx index,
- rtx (*gen_fn)(rtx, rtx, rtx))
-{
- gcc_assert ((GET_MODE (src) == V2DImode && GET_MODE (dest) == DImode)
- || (GET_MODE (src) == V2DFmode && GET_MODE (dest) == DFmode));
-
- /* Note that low is always from the lower index, and high is always
- from the higher index. */
- rtx low = loongarch_subword (dest, false);
- rtx high = loongarch_subword (dest, true);
- rtx new_src = simplify_gen_subreg (V4SImode, src, GET_MODE (src), 0);
-
- emit_insn (gen_fn (low, new_src, GEN_INT (INTVAL (index) * 2)));
- emit_insn (gen_fn (high, new_src, GEN_INT (INTVAL (index) * 2 + 1)));
-}
-
-/* Split a INSERT.D with operand DEST, SRC1.INDEX and SRC2. */
-
-void
-loongarch_split_lsx_insert_d (rtx dest, rtx src1, rtx index, rtx src2)
-{
- int i;
- gcc_assert (GET_MODE (dest) == GET_MODE (src1));
- gcc_assert ((GET_MODE (dest) == V2DImode
- && (GET_MODE (src2) == DImode || src2 == const0_rtx))
- || (GET_MODE (dest) == V2DFmode && GET_MODE (src2) == DFmode));
-
- /* Note that low is always from the lower index, and high is always
- from the higher index. */
- rtx low = loongarch_subword (src2, false);
- rtx high = loongarch_subword (src2, true);
- rtx new_dest = simplify_gen_subreg (V4SImode, dest, GET_MODE (dest), 0);
- rtx new_src1 = simplify_gen_subreg (V4SImode, src1, GET_MODE (src1), 0);
- i = exact_log2 (INTVAL (index));
- gcc_assert (i != -1);
-
- emit_insn (gen_lsx_vinsgr2vr_w (new_dest, low, new_src1,
- GEN_INT (1 << (i * 2))));
- emit_insn (gen_lsx_vinsgr2vr_w (new_dest, high, new_dest,
- GEN_INT (1 << (i * 2 + 1))));
-}
-
-/* Split FILL.D. */
-
-void
-loongarch_split_lsx_fill_d (rtx dest, rtx src)
-{
- gcc_assert ((GET_MODE (dest) == V2DImode
- && (GET_MODE (src) == DImode || src == const0_rtx))
- || (GET_MODE (dest) == V2DFmode && GET_MODE (src) == DFmode));
-
- /* Note that low is always from the lower index, and high is always
- from the higher index. */
- rtx low, high;
- if (src == const0_rtx)
- {
- low = src;
- high = src;
- }
- else
- {
- low = loongarch_subword (src, false);
- high = loongarch_subword (src, true);
- }
- rtx new_dest = simplify_gen_subreg (V4SImode, dest, GET_MODE (dest), 0);
- emit_insn (gen_lsx_vreplgr2vr_w (new_dest, low));
- emit_insn (gen_lsx_vinsgr2vr_w (new_dest, high, new_dest, GEN_INT (1 << 1)));
- emit_insn (gen_lsx_vinsgr2vr_w (new_dest, high, new_dest, GEN_INT (1 << 3)));
-}
-
-
/* Return the appropriate instructions to move SRC into DEST. Assume
that SRC is operand 1 and DEST is operand 0. */
diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md
index 87d3e7c5d9f..454cda47876 100644
--- a/gcc/config/loongarch/lsx.md
+++ b/gcc/config/loongarch/lsx.md
@@ -582,28 +582,11 @@ (define_insn "lsx_vinsgr2vr_<lsxfmt>"
(match_operand 3 "const_<bitmask>_operand" "")))]
"ISA_HAS_LSX"
{
- if (!TARGET_64BIT && (<MODE>mode == V2DImode || <MODE>mode == V2DFmode))
- return "#";
- else
- return "vinsgr2vr.<lsxfmt>\t%w0,%z1,%y3";
+ return "vinsgr2vr.<lsxfmt>\t%w0,%z1,%y3";
}
[(set_attr "type" "simd_insert")
(set_attr "mode" "<MODE>")])
-(define_split
- [(set (match_operand:LSX_D 0 "register_operand")
- (vec_merge:LSX_D
- (vec_duplicate:LSX_D
- (match_operand:<UNITMODE> 1 "<LSX_D:lsx_d>_operand"))
- (match_operand:LSX_D 2 "register_operand")
- (match_operand 3 "const_<bitmask>_operand")))]
- "reload_completed && ISA_HAS_LSX && !TARGET_64BIT"
- [(const_int 0)]
-{
- loongarch_split_lsx_insert_d (operands[0], operands[2], operands[3],
operands[1]);
- DONE;
-})
-
(define_insn "lsx_vextrins_<lsxfmt_f>_internal"
[(set (match_operand:LSX 0 "register_operand" "=f")
(vec_merge:LSX
@@ -653,70 +636,26 @@ (define_insn "lsx_vpickve2gr_<lsxfmt_f><u>"
[(set_attr "type" "simd_copy")
(set_attr "mode" "<MODE>")])
-(define_insn_and_split "lsx_vpickve2gr_du"
+(define_insn "lsx_vpickve2gr_du"
[(set (match_operand:DI 0 "register_operand" "=r")
(vec_select:DI
(match_operand:V2DI 1 "register_operand" "f")
(parallel [(match_operand 2 "const_0_or_1_operand" "")])))]
"ISA_HAS_LSX"
-{
- if (TARGET_64BIT)
- return "vpickve2gr.du\t%0,%w1,%2";
- else
- return "#";
-}
- "reload_completed && ISA_HAS_LSX && !TARGET_64BIT"
- [(const_int 0)]
-{
- loongarch_split_lsx_copy_d (operands[0], operands[1], operands[2],
- gen_lsx_vpickve2gr_wu);
- DONE;
-}
+ "vpickve2gr.du\t%0,%w1,%2"
[(set_attr "type" "simd_copy")
(set_attr "mode" "V2DI")])
-(define_insn_and_split "lsx_vpickve2gr_<lsxfmt_f>"
+(define_insn "lsx_vpickve2gr_<lsxfmt_f>"
[(set (match_operand:<UNITMODE> 0 "register_operand" "=r")
(vec_select:<UNITMODE>
(match_operand:LSX_D 1 "register_operand" "f")
(parallel [(match_operand 2 "const_<indeximm>_operand" "")])))]
"ISA_HAS_LSX"
-{
- if (TARGET_64BIT)
- return "vpickve2gr.<lsxfmt>\t%0,%w1,%2";
- else
- return "#";
-}
- "reload_completed && ISA_HAS_LSX && !TARGET_64BIT"
- [(const_int 0)]
-{
- loongarch_split_lsx_copy_d (operands[0], operands[1], operands[2],
- gen_lsx_vpickve2gr_w);
- DONE;
-}
+ "vpickve2gr.<lsxfmt>\t%0,%w1,%2"
[(set_attr "type" "simd_copy")
(set_attr "mode" "<MODE>")])
-
-(define_expand "abs<mode>2"
- [(match_operand:ILSX 0 "register_operand" "=f")
- (abs:ILSX (match_operand:ILSX 1 "register_operand" "f"))]
- "ISA_HAS_LSX"
-{
- if (ISA_HAS_LSX)
- {
- emit_insn (gen_vabs<mode>2 (operands[0], operands[1]));
- DONE;
- }
- else
- {
- rtx reg = gen_reg_rtx (<MODE>mode);
- emit_move_insn (reg, CONST0_RTX (<MODE>mode));
- emit_insn (gen_lsx_vadda_<lsxfmt> (operands[0], operands[1], reg));
- DONE;
- }
-})
-
(define_expand "neg<mode>2"
[(set (match_operand:ILSX 0 "register_operand")
(neg:ILSX (match_operand:ILSX 1 "register_operand")))]
@@ -1369,25 +1308,11 @@ (define_insn "lsx_vreplgr2vr_<lsxfmt_f>"
if (which_alternative == 1)
return "vldi.<lsxfmt>\t%w0,0";
- if (!TARGET_64BIT && (<MODE>mode == V2DImode || <MODE>mode == V2DFmode))
- return "#";
- else
- return "vreplgr2vr.<lsxfmt>\t%w0,%z1";
+ return "vreplgr2vr.<lsxfmt>\t%w0,%z1";
}
[(set_attr "type" "simd_fill")
(set_attr "mode" "<MODE>")])
-(define_split
- [(set (match_operand:LSX_D 0 "register_operand")
- (vec_duplicate:LSX_D
- (match_operand:<UNITMODE> 1 "register_operand")))]
- "reload_completed && ISA_HAS_LSX && !TARGET_64BIT"
- [(const_int 0)]
-{
- loongarch_split_lsx_fill_d (operands[0], operands[1]);
- DONE;
-})
-
(define_insn "logb<mode>2"
[(set (match_operand:FLSX 0 "register_operand" "=f")
(unspec:FLSX [(match_operand:FLSX 1 "register_operand" "f")]
@@ -2428,7 +2353,7 @@ (define_insn "vandn<mode>3"
[(set_attr "type" "simd_logic")
(set_attr "mode" "<MODE>")])
-(define_insn "vabs<mode>2"
+(define_insn "abs<mode>2"
[(set (match_operand:ILSX 0 "register_operand" "=f")
(abs:ILSX (match_operand:ILSX 1 "register_operand" "f")))]
"ISA_HAS_LSX"
diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-abs.c
b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-abs.c
new file mode 100644
index 00000000000..cf971badb51
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-abs.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mlsx" } */
+/* { dg-final { scan-assembler-times "vsigncov.w" 1 } } */
+/* { dg-final { scan-assembler-times "vsigncov.d" 1 } } */
+
+int a[4], b[4];
+
+extern int abs (int);
+
+void
+foo1 (void)
+{
+ for (int i = 0; i < 4; i++)
+ a[i] = abs (b[i]);
+}
+
+long la[2], lb[2];
+
+extern long labs (long);
+
+void
+foo2 (void)
+{
+ for (int i = 0; i < 2; i++)
+ la[i] = labs (lb[i]);
+}
