Re: [PATCH][AArch64][wwwdocs] Summarise some more AArch64 changes for GCC6

[Gerald Pfeifer]

On Wed, 27 Apr 2016, Kyrill Tkachov wrote:
> Thanks, I've incorporated your and James' feedback.
> Since James ok'd the content of the patch from an AArch64 perspective
> I'll commit this later today if I receive no further feedback.

Thanks, Kyrill, those were quite some additions!

I made a few follow-up changes to simplify things (and avoided
calling -mcpu=native a new option, since it already exists for
other targets).

Applied.

Gerald

Index: gcc-6/changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-6/changes.html,v
retrieving revision 1.97
diff -u -r1.97 changes.html
--- gcc-6/changes.html  11 Mar 2017 22:48:21 -  1.97
+++ gcc-6/changes.html  18 Mar 2017 22:36:07 -
@@ -392,11 +392,11 @@

  
A number of AArch64-specific options have been added.  The most
-   important ones are summarised in this section but for usage
-   instructions please refer to the documentation.
+   important ones are summarised in this section; for more detailed
+   information please refer to the documentation.
  
  
-   The new command-line options -march=native,
+   The command-line options -march=native,
-mcpu=native and -mtune=native are now
available on native AArch64 GNU/Linux systems.  Specifying
these options causes GCC to auto-detect the host CPU and
@@ -470,14 +470,14 @@
  
  
Improvements in the generation of conditional branches and literal
-   pools were made to allow the compiler to compile functions of a large
+   pools allow the compiler to compile functions of a large
size.  Constant pools are now placed into separate rodata sections.
-   The new option -mpc-relative-literal-loads is
-   introduced to generate per-function literal pools, limiting the maximum
+   The new option -mpc-relative-literal-loads
+   generates per-function literal pools, limiting the maximum
size of functions to 1MiB.
  
  
-   Several correctness issues with generation of Advanced SIMD instructions
+   Several correctness issues generating Advanced SIMD instructions
for big-endian targets have been fixed resulting in improved code
generation for ACLE intrinsics with -mbig-endian.
  

Re: [PATCH][AArch64][wwwdocs] Summarise some more AArch64 changes for GCC6

[Gerald Pfeifer]

Hi Sandra,

On Sun, 24 Apr 2016, Sandra Loosemore wrote:
> I haven't done a careful review of the whole section of existing text, 
> but I did notice a few things in text not being touched by this patch:

I noticed not all of the changes you recommended actually have been
made, of which I now take care by applying the patch below (finally).

Thanks for your, as usual, good feedback!

Gerald

Index: gcc-6/changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-6/changes.html,v
retrieving revision 1.92
diff -u -r1.92 changes.html
--- gcc-6/changes.html  2 Feb 2017 21:48:31 -   1.92
+++ gcc-6/changes.html  18 Feb 2017 22:13:42 -
@@ -723,8 +723,8 @@
 
 The new command-line options -march=native,
   and -mtune=native are now available on native IBM
-  z Systems.  Specifying these options will cause GCC to
-  auto-detect the host CPU and rewrite these options to the
+  z Systems.  Specifying these options causes GCC to
+  auto-detect the host CPU and choose the
   optimal setting for that system.  If GCC is unable to detect
   the host CPU these options have no effect.
 

Re: [PATCH][AArch64][wwwdocs] Summarise some more AArch64 changes for GCC6

[Kyrill Tkachov]

On 27/04/16 18:14, Jim Wilson wrote:

On Wed, Apr 27, 2016 at 3:33 AM, Kyrill Tkachov
 wrote:

Thanks, I've incorporated your and James' feedback.
Since James ok'd the content of the patch from an AArch64 perspective
I'll commit this later today if I receive no further feedback.

There is no paragraph for the Qualcomm qdf24xx.  Do you want me to
write that and submit it?  That could take a while as I will have to
discuss if with Qualcomm first.


Hi Jim,

I'll add one separately (and an entry in the ARM section too).
Sorry for the delay,

Kyrill


Jim

Re: [PATCH][AArch64][wwwdocs] Summarise some more AArch64 changes for GCC6

[Jim Wilson]

On Wed, Apr 27, 2016 at 3:33 AM, Kyrill Tkachov
 wrote:
> Thanks, I've incorporated your and James' feedback.
> Since James ok'd the content of the patch from an AArch64 perspective
> I'll commit this later today if I receive no further feedback.

There is no paragraph for the Qualcomm qdf24xx.  Do you want me to
write that and submit it?  That could take a while as I will have to
discuss if with Qualcomm first.

Jim

Re: [PATCH][AArch64][wwwdocs] Summarise some more AArch64 changes for GCC6

[Kyrill Tkachov]

On 25/04/16 02:43, Sandra Loosemore wrote:

On 04/22/2016 03:57 AM, James Greenhalgh wrote:

On Thu, Apr 21, 2016 at 09:15:17AM +0100, Kyrill Tkachov wrote:

Hi all,

Here's a proposed summary of the changes in the AArch64 backend for GCC 6.
If there's anything I've missed it's purely my oversight, feel free to add
entries or suggest improvements.


For me, I'm mostly happy with the wording below (I've tried to be
helpful inline). But I'm not as conscientious at checking grammar as others
in the community. So this is OK from an AArch64 target perspective with
the changes below, but wait a short while to give Gerald or Sandra a chance
to comment.


I haven't done a careful review of the whole section of existing text, but I 
did notice a few things in text not being touched by this patch:


+ 
 The new command line options -march=native,


s/command line options/command-line options/


-mcpu=native and -mtune=native are now
 available on native AArch64 GNU/Linux systems. Specifying
 these options will cause GCC to auto-detect the host CPU and


s/will cause/causes/


 rewrite these options to the optimal setting for that system.


s/rewrite these options to the optimal/choose the/


-   -fpic is now supported by the AArch64 target when 
generating
+   -fpic is now supported when generating
 code for the small code model (-mcmodel=small).  The size 
of
 the global offset table (GOT) is limited to 28KiB under the LP64 SysV 
ABI
 , and 15KiB under the ILP32 SysV ABI.


Move the comma directly after "ABI", not separated by newline and whitespace.



Thanks, I've incorporated your and James' feedback.
Since James ok'd the content of the patch from an AArch64 perspective
I'll commit this later today if I receive no further feedback.

Thanks,
Kyrill


-Sandra



Index: htdocs/gcc-6/changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-6/changes.html,v
retrieving revision 1.73
diff -U 3 -r1.73 changes.html
--- htdocs/gcc-6/changes.html	7 Apr 2016 09:38:31 -	1.73
+++ htdocs/gcc-6/changes.html	25 Apr 2016 09:10:25 -
@@ -328,29 +328,90 @@
 AArch64

  
-   The new command line options -march=native,
+   A number of AArch64-specific options have been added.  The most
+   important ones are summarised in this section but for usage
+   instructions please refer to the documentation.
+ 
+ 
+   The new command-line options -march=native,
-mcpu=native and -mtune=native are now
available on native AArch64 GNU/Linux systems.  Specifying
-   these options will cause GCC to auto-detect the host CPU and
-   rewrite these options to the optimal setting for that system.
-   If GCC is unable to detect the host CPU these options have no effect.
+   these options causes GCC to auto-detect the host CPU and
+   choose the optimal setting for that system.
  
  
-   -fpic is now supported by the AArch64 target when generating
+   -fpic is now supported when generating
code for the small code model (-mcmodel=small).  The size of
-   the global offset table (GOT) is limited to 28KiB under the LP64 SysV ABI
-   , and 15KiB under the ILP32 SysV ABI.
+   the global offset table (GOT) is limited to 28KiB under the LP64
+   SysV ABI, and 15KiB under the ILP32 SysV ABI.
  
  
-   The AArch64 port now supports target attributes and pragmas.  Please
-   refer to the https://gcc.gnu.org/onlinedocs/gcc/AArch64-Function-Attributes.html#AArch64-Function-Attributes;>
-   documentation for details of available attributes and
+   Target attributes and pragmas are now supported.  Please
+   refer to the documentation for details of available attributes and
pragmas as well as usage instructions.
  
  
Link-time optimization across translation units with different
target-specific options is now supported.
  
+ 
+   The option -mtls-size= is now supported.  It can be used to
+   specify the bit size of TLS offsets, allowing GCC to generate
+   better TLS instruction sequences.
+ 
+ 
+   The option -fno-plt is now fully functional.
+ 
+ 
+   The ARMv8.1-A architecture and the Large System Extensions are now
+   supported.  They can be used by specifying the
+   -march=armv8.1-a option.  Additionally, the
+   +lse option extension can be used in a similar fashion
+   to other option extensions.
+   The Large System Extensions introduce new instructions that are used
+   in the implementation of atomic operations.
+ 
+ 
+   The ACLE half-precision floating-point type __fp16 is now
+   supported in the C and C++ languages.
+ 
+ 
+   The ARM Cortex-A35 processor is now supported via the
+   -mcpu=cortex-a35 and -mtune=cortex-a35
+   options as well as 

Re: [PATCH][AArch64][wwwdocs] Summarise some more AArch64 changes for GCC6

[Jim Wilson]

On Thu, Apr 21, 2016 at 1:15 AM, Kyrill Tkachov
 wrote:
> Jim, you added support for the qdf24xx identifier to -mcpu and -mtune.
> Could you please suggest an appropriate entry to describe it?
> I think the same format as the Cortex-A35 entry in this patch would be
> appropriate.

This is tricky, as I'm working under an NDA, and the NDA requires
pre-approval from Qualcomm for each patch I contribute that is related
to this project.  It is actually easier if someone else can add this
text.
 The Cortex-A35 entry does look appropriate, with "ARM Cortex-A35"
replaced with "Qualcomm QDF24xx".  If you want me to write the text, I
will have to go through the approval process, which may take some
time.

Jim

Re: [PATCH][AArch64][wwwdocs] Summarise some more AArch64 changes for GCC6

[Evandro Menezes]

On 04/21/16 03:15, Kyrill Tkachov wrote:

Ok to commit?


LGTM

--
Evandro Menezes

Re: [PATCH][AArch64][wwwdocs] Summarise some more AArch64 changes for GCC6

[Sandra Loosemore]

On 04/22/2016 03:57 AM, James Greenhalgh wrote:

On Thu, Apr 21, 2016 at 09:15:17AM +0100, Kyrill Tkachov wrote:

Hi all,

Here's a proposed summary of the changes in the AArch64 backend for GCC 6.
If there's anything I've missed it's purely my oversight, feel free to add
entries or suggest improvements.


For me, I'm mostly happy with the wording below (I've tried to be
helpful inline). But I'm not as conscientious at checking grammar as others
in the community. So this is OK from an AArch64 target perspective with
the changes below, but wait a short while to give Gerald or Sandra a chance
to comment.


I haven't done a careful review of the whole section of existing text, 
but I did notice a few things in text not being touched by this patch:



+ 
 The new command line options -march=native,


s/command line options/command-line options/


 -mcpu=native and -mtune=native are now
 available on native AArch64 GNU/Linux systems.  Specifying
 these options will cause GCC to auto-detect the host CPU and


s/will cause/causes/


 rewrite these options to the optimal setting for that system.


s/rewrite these options to the optimal/choose the/


-   -fpic is now supported by the AArch64 target when 
generating
+   -fpic is now supported when generating
 code for the small code model (-mcmodel=small).  The size 
of
 the global offset table (GOT) is limited to 28KiB under the LP64 SysV 
ABI
 , and 15KiB under the ILP32 SysV ABI.


Move the comma directly after "ABI", not separated by newline and 
whitespace.


-Sandra

Re: [PATCH][AArch64][wwwdocs] Summarise some more AArch64 changes for GCC6

[James Greenhalgh]

On Thu, Apr 21, 2016 at 09:15:17AM +0100, Kyrill Tkachov wrote:
> Hi all,
> 
> Here's a proposed summary of the changes in the AArch64 backend for GCC 6.
> If there's anything I've missed it's purely my oversight, feel free to add
> entries or suggest improvements.

For me, I'm mostly happy with the wording below (I've tried to be
helpful inline). But I'm not as conscientious at checking grammar as others
in the community. So this is OK from an AArch64 target perspective with
the changes below, but wait a short while to give Gerald or Sandra a chance
to comment.

> Index: htdocs/gcc-6/changes.html
> ===
> RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-6/changes.html,v
> retrieving revision 1.62
> diff -U 3 -r1.62 changes.html
> --- htdocs/gcc-6/changes.html 24 Feb 2016 09:36:06 -  1.62
> +++ htdocs/gcc-6/changes.html 12 Apr 2016 12:47:30 -
> @@ -312,29 +312,91 @@
>  AArch64
> 
>   
> +   A number of AArch64-specific options were added.  The most important

"were" is in a different tense to the other entries in this list. To match,
you might want to use

  A number of AArch64-specific options have been added.

Or:

  A number of AArch64-specific options are now supported.

> +   ones are summarised in this section but for usage instructions please
> +   refer to the documentation.
> + 
> + 
> The new command line options -march=native,
> -mcpu=native and -mtune=native are now
> available on native AArch64 GNU/Linux systems.  Specifying
> these options will cause GCC to auto-detect the host CPU and
> rewrite these options to the optimal setting for that system.
> -   If GCC is unable to detect the host CPU these options have no effect.
>   
>   
> -   -fpic is now supported by the AArch64 target when 
> generating
> +   -fpic is now supported when generating
> code for the small code model (-mcmodel=small).  The 
> size of
> the global offset table (GOT) is limited to 28KiB under the LP64 SysV 
> ABI
> , and 15KiB under the ILP32 SysV ABI.
>   
>   
> -   The AArch64 port now supports target attributes and pragmas.  Please
> -   refer to the  href="https://gcc.gnu.org/onlinedocs/gcc/AArch64-Function-Attributes.html#AArch64-Function-Attributes;>
> -   documentation for details of available attributes and
> +   Target attributes and pragmas are now supported.  Please
> +   refer to the documentation for details of available attributes and
> pragmas as well as usage instructions.
>   
>   
> Link-time optimization across translation units with different
> target-specific options is now supported.
>   
> + 
> +   The option -mtls-size= is now supported.  It can be used 
> to
> +   specify the bit size of TLS offsets, allowing GCC to generate
> +   better TLS instruction sequences.
> + 
> + 
> +   The option -fno-plt is now fixed and is fully
> +   functional.

Remove "is now fixed" ?

> + 
> + 
> +   The ARMv8.1-A architecture and the Large System Extensions are now
> +   supported.  They can be used by specifying the
> +   -march=armv8.1-a option.  Additionally, the
> +   +lse option extension can be used in a similar fashion
> +   to other option extensions.
> +   The Large System Extensions introduce new instructions that are used
> +   in the implementation of common atomic operations.

Remove "common"

Thanks,
James