Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code
Hi,
I'm going to commit the attached. Thanks Lehua for reporting.
Regards
Robin
>From 1a4dfe90f251e38e27104f2fa11feecd3b04c4c1 Mon Sep 17 00:00:00 2001
From: Robin Dapp
Date: Tue, 20 Jun 2023 15:52:16 +0200
Subject: [PATCH] RISC-V: testsuite: Add missing -mabi=lp64d.
This fixes more cases of missing -mabi=lp64d.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c: Add
-mabi=lp64d.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c: Dito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c: Dito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c: Dito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c: Dito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c: Dito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c: Dito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c: Dito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c: Dito.
---
.../gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c | 2 +-
9 files changed, 9 insertions(+), 9 deletions(-)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
index c32c31ecd69..9ed7c4f1205 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b
-fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
+/* { dg-additional-options "-std=c99 -O3 -march=rv64gcv_zvl128b -mabi=lp64d
-fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */
#include
#include
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c
index 34efd5f700a..9cb167a8cdc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic
-Wno-psabi" } */
#include
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c
index 5f3168a320a..2837ff58e2d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic
-Wno-psabi" } */
#include
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c
index 7210327a4ff..47f30ed79f1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic
-Wno-psabi" } */
#include
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c
index c5cb56a88c7..f7169f07506 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -mabi=lp64d -Wno-pedantic
-Wno-psabi" } */
#include
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c
index 28f11150f8f..3d60e635869 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c
+++
Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code
> By the way, shouldn't these cases have the `-mabi=lp64d` option added, > otherwise I get the following failure message when I run tests on RV32 GCC. > > FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c -std=c99 -O3 > -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax (test for > excess errors) > Excess errors. > cc1: error: ABI requires '-march=rv32' Arg, yes definitely, sorry. I keep forgetting this... Will fix. Regards Robin
Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi"
} */
By the way, shouldn't these cases have the `-mabi=lp64d` option added,
otherwise I get the following failure message when I run tests on RV32 GCC.
FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c -std=c99 -O3
-ftree-vectorize --param riscv-autovec-preference=fixed-vlmax (test for excess
errors)
Excess errors.
cc1: error: ABI requires '-march=rv32'
Best,
Lehua
--Original--
From: "RobinDapp"
Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code
Actually they are already in for a bit :)
51795b910737 (Robin Dapp 2023-06-01 14:18:57 +0200 1) /* { dg-do
compile } */
I thought something is special about them that they somehow didn't run
on your machine or so.
The time I just said is your commit time from this link
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=51795b91073798c718df6fafb01303861641a5af.
authorRobin Dapp
Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code
> Oh, I should know why. These cases of yours were added yesterday,
> while I submitted the patch the day before, and then yesterday by Pan
> to help me merge in after your cases. Sorry for introducing this issue,
> I'll submit a new fix patch.
Actually they are already in for a bit :)
51795b910737 (Robin Dapp 2023-06-01 14:18:57 +0200 1) /* { dg-do compile } */
I thought something is special about them that they somehow didn't run
on your machine or so.
But no need for a new patch, thanks. I already have it and will commit
it soon.
Regards
Robin
Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code
Lehua, would they not show up in your test runs? You fixed several other tests but these somehow not? Oh, I should know why. These cases of yours were added yesterday, while I submitted the patch the day before, and then yesterday by Pan to help me merge in after your cases. Sorry for introducing this issue, I'll submit a new fix patch. Best, Lehua
Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code
> Committed, thanks Jeff.
The vec_set/vec_extract tests FAIL since this commit. I'm going to
commit the attached as obvious.
Lehua, would they not show up in your test runs? You fixed several
other tests but these somehow not?
Regards
Robin
Subject: [PATCH] RISC-V: testsuite: Add -Wno-psabi to vec_set/vec_extract
testcases.
This fixes some fallout from the recent psabi changes.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c: Add
-Wno-psabi.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c: Dito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c: Dito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c: Dito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c:
Dito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c: Dito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c: Dito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c: Dito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c: Dito.
* gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c: Dito.
---
.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c| 2 +-
.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c | 2 +-
.../gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c| 2 +-
10 files changed, 10 insertions(+), 10 deletions(-)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c
index 1a6e6dd83ee..34efd5f700a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
#include
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c
index 884c38e0bd8..5f3168a320a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
#include
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c
index 844ad392df0..7210327a4ff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
#include
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c
index 04c234e7d2d..c5cb56a88c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic" } */
+/* { dg-additional-options "-march=rv64gcv_zvfh -Wno-pedantic -Wno-psabi" } */
#include
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c
index dd22dae5eb9..43110c0bb8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c
@@ -1,5 +1,5 @@
/* { dg-do run { target { riscv_vector } } } */
-/* { dg-additional-options "-std=c99 -Wno-pedantic" } */
+/* { dg-additional-options "-std=c99 -Wno-pedantic -Wno-psabi" } */
#include
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c
index 4fb4e822b93..28f11150f8f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c
+++
RE: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code
Committed, thanks Jeff. -Original Message- From: Gcc-patches On Behalf Of Jeff Law via Gcc-patches Sent: Tuesday, June 20, 2023 2:04 AM To: 钟居哲 ; 丁乐华 ; gcc-patches Cc: Wang, Yanzhang ; kito.cheng ; palmer ; rdapp.gcc Subject: Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code On 6/18/23 07:16, 钟居哲 wrote: > Thanks for cleaning up codes for future's ABI support patch. > Let's wait for Jeff or Robin comments. Looks reasonable to me given the state we're in WRT psabi and vectors. jeff
Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code
On 6/18/23 07:16, 钟居哲 wrote: Thanks for cleaning up codes for future's ABI support patch. Let's wait for Jeff or Robin comments. Looks reasonable to me given the state we're in WRT psabi and vectors. jeff
Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code
Thanks for cleaning up codes for future's ABI support patch. Let's wait for Jeff or Robin comments. Thanks. juzhe.zh...@rivai.ai From: Lehua Ding Date: 2023-06-18 19:41 To: gcc-patches CC: juzhe.zhong; yanzhang.wang; kito.cheng; palmer; jeffreyalaw Subject: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code Hi, This patch does several things: 1. Adds the missed checking of tuple vector mode 2. Extend the scope of checking to all vector types, previously it was only for scalable vector types. 3. Simplify the logic of determining code of vector type which will lower to vector tmode code Best, Lehua gcc/ChangeLog: * config/riscv/riscv.cc (riscv_scalable_vector_type_p): Delete. (riscv_arg_has_vector): Simplify. (riscv_pass_in_vector_p): Adjust warning message. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/fixed-vlmax-1.c: Add -Wno-psabi option. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-1.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-2.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-3.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-4.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-5.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-6.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge-7.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm-1.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm-2.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm-3.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm-4.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm-5.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm-6.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm-7.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Ditto. * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Ditto. * gcc.target/riscv/rvv/base/pr110119-1.c: Ditto. * gcc.target/riscv/rvv/base/pr110119-2.c: Ditto. * gcc.target/riscv/vector-abi-1.c: Ditto. * gcc.target/riscv/vector-abi-2.c: Ditto. * gcc.target/riscv/vector-abi-3.c: Ditto. * gcc.target/riscv/vector-abi-4.c: Ditto. * gcc.target/riscv/vector-abi-5.c: Ditto. * gcc.target/riscv/vector-abi-6.c: Ditto. * gcc.target/riscv/vector-abi-7.c: New test. * gcc.target/riscv/vector-abi-8.c: New test. * gcc.target/riscv/vector-abi-9.c: New test. --- gcc/config/riscv/riscv.cc | 53 ++- .../riscv/rvv/autovec/fixed-vlmax-1.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge-1.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge-2.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge-3.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge-4.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge-5.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge-6.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge-7.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge_run-1.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge_run-2.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge_run-3.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge_run-4.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge_run-5.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge_run-6.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/merge_run-7.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm-1.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm-2.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm-3.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm-4.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm-5.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm-6.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm-7.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm_run-1.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm_run-2.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm_run-3.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm_run-4.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm_run-5.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm_run-6.c | 2 +- .../riscv/rvv/autovec/vls-vlmax/perm_run-7.c | 2 +- .../gcc.target/riscv/rvv/base/pr110119-1.c| 2 +- .../gcc.target/riscv/rvv/base/pr110119-2.c| 2 +- gcc/testsuite/gcc.target/riscv/vector-abi-1.c | 2 +- gcc/testsuite/gcc.target/riscv/vector-abi-2.c | 2 +-
