Re: [PATCH v6] RISC-V: Add support for experimental zfa extension.
FYI: This PR described the syntax of fli instruction, which is implemented in LLVM, and the latest binutils patch (IIRC :P): https://github.com/riscv-non-isa/riscv-asm-manual/pull/85
Re: [PATCH v6] RISC-V: Add support for experimental zfa extension.
On 3/10/23 05:40, Jin Ma via Gcc-patches wrote: This patch adds the 'Zfa' extension for riscv, which is based on: https://github.com/riscv/riscv-isa-manual/commit/d74d99e22d5f68832f70982d867614e2149a3bd7 latest 'Zfa' change on the master branch of the RISC-V ISA Manual as of this writing. The Wiki Page (details): https://github.com/a4lg/binutils-gdb/wiki/riscv_zfa The binutils-gdb for 'Zfa' extension: https://sourceware.org/pipermail/binutils/2022-September/122938.html Implementation of zfa extension on LLVM: https://reviews.llvm.org/rGc0947dc44109252fcc0f68a542fc6ef250d4d3a9 There are three points that need to be discussed here. 1. According to riscv-spec, "The FCVTMO D.W.D instruction was added principally to accelerate the processing of JavaScript Numbers.", so it seems that no implementation is required in the compiler. 2. The FROUND and FROUNDN instructions in this patch use related functions in the math library, such as round, floor, ceil, etc. Since there is no interface for half-precision in the math library, the instructions FROUN D.H and FROUNDN X.H have not been implemented for the time being. Is it necessary to add a built-in interface belonging to riscv such as __builtin_roundhf or __builtin_roundf16 to generate half floating point instructions? 3. As far as I know, FMINM and FMAXM instructions correspond to C23 library function fminimum and fmaximum. Therefore, I have not dealt with such instructions for the time being, but have simply implemented the pattern of fminm3 and fmaxm3. Is it necessary to add a built-in interface belonging to riscv such as__builtin_fminm to generate half floating-point instructions? gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add zfa extension. * config/riscv/constraints.md (Zf): Constrain the floating point number that the FLI instruction can load. * config/riscv/iterators.md (round_pattern): New. * config/riscv/predicates.md: Predicate the floating point number that the FLI instruction can load. * config/riscv/riscv-opts.h (MASK_ZFA): New. (TARGET_ZFA): New. * config/riscv/riscv-protos.h (riscv_float_const_rtx_index_for_fli): Get the index of the floating-point number that the FLI instruction can load. * config/riscv/riscv.cc (find_index_in_array): New. (riscv_float_const_rtx_index_for_fli): New. (riscv_cannot_force_const_mem): Likewise. (riscv_const_insns): Likewise. (riscv_legitimize_const_move): Likewise. (riscv_split_64bit_move_p): Exclude floating point numbers that can be loaded by FLI instructions. (riscv_output_move): Likewise. (riscv_memmodel_needs_release_fence): Likewise. (riscv_print_operand): Likewise. (riscv_secondary_memory_needed): Likewise. * config/riscv/riscv.h (GP_REG_RTX_P): New. * config/riscv/riscv.md (fminm3): New. (fmaxm3): New. (2): New. (rint2): New. (f_quiet4_zfa): New. gcc/testsuite/ChangeLog: * gcc.target/riscv/zfa-fleq-fltq-rv32.c: New test. * gcc.target/riscv/zfa-fleq-fltq.c: New test. * gcc.target/riscv/zfa-fli-rv32.c: New test. * gcc.target/riscv/zfa-fli-zfh-rv32.c: New test. * gcc.target/riscv/zfa-fli-zfh.c: New test. * gcc.target/riscv/zfa-fli.c: New test. * gcc.target/riscv/zfa-fmovh-fmovp-rv32.c: New test. * gcc.target/riscv/zfa-fround-rv32.c: New test. * gcc.target/riscv/zfa-fround.c: New test. --- gcc/common/config/riscv/riscv-common.cc | 4 + gcc/config/riscv/constraints.md | 7 + gcc/config/riscv/iterators.md | 5 + gcc/config/riscv/predicates.md| 4 + gcc/config/riscv/riscv-opts.h | 3 + gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv.cc | 168 +- gcc/config/riscv/riscv.h | 1 + gcc/config/riscv/riscv.md | 112 +--- .../gcc.target/riscv/zfa-fleq-fltq-rv32.c | 19 ++ .../gcc.target/riscv/zfa-fleq-fltq.c | 19 ++ gcc/testsuite/gcc.target/riscv/zfa-fli-rv32.c | 79 .../gcc.target/riscv/zfa-fli-zfh-rv32.c | 41 + gcc/testsuite/gcc.target/riscv/zfa-fli-zfh.c | 41 + gcc/testsuite/gcc.target/riscv/zfa-fli.c | 79 .../gcc.target/riscv/zfa-fmovh-fmovp-rv32.c | 10 ++ .../gcc.target/riscv/zfa-fround-rv32.c| 42 + gcc/testsuite/gcc.target/riscv/zfa-fround.c | 42 + 18 files changed, 654 insertions(+), 23 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fleq-fltq-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fleq-fltq.c create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-zfh-rv32.c create mode
Re: [PATCH v6] RISC-V: Add support for experimental zfa extension.
Thank you very much for your comments. Since a long time has passed and this is an initial version, I will update this patch. -- From:Christoph Müllner Sent At:2023 Apr. 13 (Thu.) 17:22 To:Jin Ma Cc:gcc-patches ; kito.cheng ; kito.cheng ; palmer Subject:Re: [PATCH v6] RISC-V: Add support for experimental zfa extension. On Fri, Mar 10, 2023 at 1:41 PM Jin Ma via Gcc-patches wrote: > > This patch adds the 'Zfa' extension for riscv, which is based on: > https://github.com/riscv/riscv-isa-manual/commit/d74d99e22d5f68832f70982d867614e2149a3bd7 > latest 'Zfa' change on the master branch of the RISC-V ISA Manual as > of this writing. > > The Wiki Page (details): > https://github.com/a4lg/binutils-gdb/wiki/riscv_zfa > > The binutils-gdb for 'Zfa' extension: > https://sourceware.org/pipermail/binutils/2022-September/122938.html > > Implementation of zfa extension on LLVM: > https://reviews.llvm.org/rGc0947dc44109252fcc0f68a542fc6ef250d4d3a9 > > There are three points that need to be discussed here. > 1. According to riscv-spec, "The FCVTMO D.W.D instruction was added > principally to > accelerate the processing of JavaScript Numbers.", so it seems that no > implementation > is required in the compiler. > 2. The FROUND and FROUNDN instructions in this patch use related functions in > the math > library, such as round, floor, ceil, etc. Since there is no interface for > half-precision in > the math library, the instructions FROUN D.H and FROUNDN X.H have not been > implemented for > the time being. Is it necessary to add a built-in interface belonging to > riscv such as > __builtin_roundhf or __builtin_roundf16 to generate half floating point > instructions? > 3. As far as I know, FMINM and FMAXM instructions correspond to C23 library > function fminimum > and fmaximum. Therefore, I have not dealt with such instructions for the time > being, but have > simply implemented the pattern of fminm3 and fmaxm3. Is > it necessary to > add a built-in interface belonging to riscv such as__builtin_fminm to > generate half > floating-point instructions? I have rebased and tested this patch. Here are my observations (with fixes below at the actual code): * There is a compiler warning because of a missing "fallthrough" comment * There are merge conflicts with a current master * The constant operand of the fli instruction uses the constant index in the rs1-field, but not the constant in hex FP literal form A patch that addresses these issues can also be found here: https://github.com/cmuellner/gcc/tree/riscv-zfa Additionally I observe the following failing test cases with this patch applied: === gcc: Unexpected fails for rv64gc lp64d medlow === FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O0 (internal compiler error: Segmentation fault) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O0 (test for excess errors) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O1 (internal compiler error: Segmentation fault) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O1 (test for excess errors) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O2 (internal compiler error: Segmentation fault) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O2 (test for excess errors) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O2 -flto -fno-use-linker-plugin -flto-partition=none (internal compiler error: Segmentation fault) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O2 -flto -fno-use-linker-plugin -flto-partition=none (test for excess errors) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects (internal compiler error: Segmentation fault) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects (test for excess errors) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O3 -g (internal compiler error: Segmentation fault) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O3 -g (test for excess errors) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -Os (internal compiler error: Segmentation fault) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -Os (test for excess errors) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -Og -g (internal compiler error: Segmentation fault) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -Og -g (test for excess errors) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -Oz (internal compiler error: Segmentation fault) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -Oz (test for excess errors) I have not analysed these ICEs so far. > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc: Add zfa extension. > * config/riscv/constraints.md (Zf): Constrain the floating point number that > the FLI instruction can load. > * config/riscv/iterators.md (round_pattern): New. > * config/riscv/predicates.md: Predicate the floating point number that the > FLI instruction can load. > * config/riscv/riscv-opts.h (MASK_ZFA): New. > (TARGET_ZFA): New. > * config/riscv/riscv-protos.h (riscv_float_const_rtx_index_for
Re: [PATCH v6] RISC-V: Add support for experimental zfa extension.
On Fri, Mar 10, 2023 at 1:41 PM Jin Ma via Gcc-patches wrote: > > This patch adds the 'Zfa' extension for riscv, which is based on: > > https://github.com/riscv/riscv-isa-manual/commit/d74d99e22d5f68832f70982d867614e2149a3bd7 > latest 'Zfa' change on the master branch of the RISC-V ISA Manual as > of this writing. > > The Wiki Page (details): > https://github.com/a4lg/binutils-gdb/wiki/riscv_zfa > > The binutils-gdb for 'Zfa' extension: > https://sourceware.org/pipermail/binutils/2022-September/122938.html > > Implementation of zfa extension on LLVM: > https://reviews.llvm.org/rGc0947dc44109252fcc0f68a542fc6ef250d4d3a9 > > There are three points that need to be discussed here. > 1. According to riscv-spec, "The FCVTMO D.W.D instruction was added > principally to > accelerate the processing of JavaScript Numbers.", so it seems that no > implementation > is required in the compiler. > 2. The FROUND and FROUNDN instructions in this patch use related functions in > the math > library, such as round, floor, ceil, etc. Since there is no interface for > half-precision in > the math library, the instructions FROUN D.H and FROUNDN X.H have not been > implemented for > the time being. Is it necessary to add a built-in interface belonging to > riscv such as > __builtin_roundhf or __builtin_roundf16 to generate half floating point > instructions? > 3. As far as I know, FMINM and FMAXM instructions correspond to C23 library > function fminimum > and fmaximum. Therefore, I have not dealt with such instructions for the > time being, but have > simply implemented the pattern of fminm3 and fmaxm3. Is > it necessary to > add a built-in interface belonging to riscv such as__builtin_fminm to > generate half > floating-point instructions? I have rebased and tested this patch. Here are my observations (with fixes below at the actual code): * There is a compiler warning because of a missing "fallthrough" comment * There are merge conflicts with a current master * The constant operand of the fli instruction uses the constant index in the rs1-field, but not the constant in hex FP literal form A patch that addresses these issues can also be found here: https://github.com/cmuellner/gcc/tree/riscv-zfa Additionally I observe the following failing test cases with this patch applied: === gcc: Unexpected fails for rv64gc lp64d medlow === FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O0 (internal compiler error: Segmentation fault) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O0 (test for excess errors) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O1 (internal compiler error: Segmentation fault) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O1 (test for excess errors) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O2 (internal compiler error: Segmentation fault) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O2 (test for excess errors) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O2 -flto -fno-use-linker-plugin -flto-partition=none (internal compiler error: Segmentation fault) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O2 -flto -fno-use-linker-plugin -flto-partition=none (test for excess errors) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects (internal compiler error: Segmentation fault) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects (test for excess errors) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O3 -g (internal compiler error: Segmentation fault) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -O3 -g (test for excess errors) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -Os (internal compiler error: Segmentation fault) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -Os (test for excess errors) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -Og -g (internal compiler error: Segmentation fault) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -Og -g (test for excess errors) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -Oz (internal compiler error: Segmentation fault) FAIL: gcc.target/riscv/zero-scratch-regs-3.c -Oz (test for excess errors) I have not analysed these ICEs so far. > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc: Add zfa extension. > * config/riscv/constraints.md (Zf): Constrain the floating point > number that the FLI instruction can load. > * config/riscv/iterators.md (round_pattern): New. > * config/riscv/predicates.md: Predicate the floating point number > that the FLI instruction can load. > * config/riscv/riscv-opts.h (MASK_ZFA): New. > (TARGET_ZFA): New. > * config/riscv/riscv-protos.h (riscv_float_const_rtx_index_for_fli): > Get the index of the > floating-point number that the FLI instruction can load. > * config/riscv/riscv.cc (find_index_in_array): New. > (riscv_float_const_rtx_index_for_fli): New. > (riscv_
Re: [PATCH v6] RISC-V: Add support for experimental zfa extension.
On 3/10/23 05:40, Jin Ma via Gcc-patches wrote: This patch adds the 'Zfa' extension for riscv, which is based on: https://github.com/riscv/riscv-isa-manual/commit/d74d99e22d5f68832f70982d867614e2149a3bd7 latest 'Zfa' change on the master branch of the RISC-V ISA Manual as of this writing. The Wiki Page (details): https://github.com/a4lg/binutils-gdb/wiki/riscv_zfa The binutils-gdb for 'Zfa' extension: https://sourceware.org/pipermail/binutils/2022-September/122938.html Implementation of zfa extension on LLVM: https://reviews.llvm.org/rGc0947dc44109252fcc0f68a542fc6ef250d4d3a9 There are three points that need to be discussed here. 1. According to riscv-spec, "The FCVTMO D.W.D instruction was added principally to accelerate the processing of JavaScript Numbers.", so it seems that no implementation is required in the compiler. 2. The FROUND and FROUNDN instructions in this patch use related functions in the math library, such as round, floor, ceil, etc. Since there is no interface for half-precision in the math library, the instructions FROUN D.H and FROUNDN X.H have not been implemented for the time being. Is it necessary to add a built-in interface belonging to riscv such as __builtin_roundhf or __builtin_roundf16 to generate half floating point instructions? 3. As far as I know, FMINM and FMAXM instructions correspond to C23 library function fminimum and fmaximum. Therefore, I have not dealt with such instructions for the time being, but have simply implemented the pattern of fminm3 and fmaxm3. Is it necessary to add a built-in interface belonging to riscv such as__builtin_fminm to generate half floating-point instructions? gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add zfa extension. * config/riscv/constraints.md (Zf): Constrain the floating point number that the FLI instruction can load. * config/riscv/iterators.md (round_pattern): New. * config/riscv/predicates.md: Predicate the floating point number that the FLI instruction can load. * config/riscv/riscv-opts.h (MASK_ZFA): New. (TARGET_ZFA): New. * config/riscv/riscv-protos.h (riscv_float_const_rtx_index_for_fli): Get the index of the floating-point number that the FLI instruction can load. * config/riscv/riscv.cc (find_index_in_array): New. (riscv_float_const_rtx_index_for_fli): New. (riscv_cannot_force_const_mem): Likewise. (riscv_const_insns): Likewise. (riscv_legitimize_const_move): Likewise. (riscv_split_64bit_move_p): Exclude floating point numbers that can be loaded by FLI instructions. (riscv_output_move): Likewise. (riscv_memmodel_needs_release_fence): Likewise. (riscv_print_operand): Likewise. (riscv_secondary_memory_needed): Likewise. * config/riscv/riscv.h (GP_REG_RTX_P): New. * config/riscv/riscv.md (fminm3): New. (fmaxm3): New. (2): New. (rint2): New. (f_quiet4_zfa): New. gcc/testsuite/ChangeLog: * gcc.target/riscv/zfa-fleq-fltq-rv32.c: New test. * gcc.target/riscv/zfa-fleq-fltq.c: New test. * gcc.target/riscv/zfa-fli-rv32.c: New test. * gcc.target/riscv/zfa-fli-zfh-rv32.c: New test. * gcc.target/riscv/zfa-fli-zfh.c: New test. * gcc.target/riscv/zfa-fli.c: New test. * gcc.target/riscv/zfa-fmovh-fmovp-rv32.c: New test. * gcc.target/riscv/zfa-fround-rv32.c: New test. * gcc.target/riscv/zfa-fround.c: New test. This needs to wait for gcc-14 IMHO. jeff
