Re: [Patch, i386] Separate Intel processor with expanded ISA
On Mon, Jan 27, 2014 at 10:15 AM, Uros Bizjak ubiz...@gmail.com wrote: +2013-12-29 Allan Sandfeld Jensen sandf...@kde.org Missing space in ChangeLog entry. + * config/i386/i386.c (get_builtin_code_for_version): Separate + Westmere from Nehalem, Ivy Bridge from Sandy Bridge and + Broadwell from Haswell. --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -31298,18 +31298,27 @@ get_builtin_code_for_version (tree decl, tree *predicate_list) priority = P_PROC_SSSE3; break; case PROCESSOR_NEHALEM: - /* We translate arch=corei7 and arch=nehelam to - corei7 so that it will be mapped to M_INTEL_COREI7 - as cpu type to cover all M_INTEL_COREI7_XXXs. */ - arg_str = corei7; + if (new_target-x_ix86_isa_flags OPTION_MASK_ISA_AES) + arg_str = westmere; + else + /* We translate arch=corei7 and arch=nehelam to Trivial typo above: arch=nehalem. OK for mainline with these changes. I have committed slightly reformated patches with following ChangeLog to mainline SVN. 2014-01-27 Allan Sandfeld Jensen sandf...@kde.org * config/i386/i386.c (get_builtin_code_for_version): Separate Westmere from Nehalem, Ivy Bridge from Sandy Bridge and Broadwell from Haswell. testsuite/ChangeLog: 2014-01-27 Allan Sandfeld Jensen sandf...@kde.org * g++.dg/ext/mv16.C: New tests. Uros.
Re: [Patch, i386] Separate Intel processor with expanded ISA
Hello! +2013-12-29 Allan Sandfeld Jensen sandf...@kde.org Missing space in ChangeLog entry. + * config/i386/i386.c (get_builtin_code_for_version): Separate + Westmere from Nehalem, Ivy Bridge from Sandy Bridge and + Broadwell from Haswell. --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -31298,18 +31298,27 @@ get_builtin_code_for_version (tree decl, tree *predicate_list) priority = P_PROC_SSSE3; break; case PROCESSOR_NEHALEM: - /* We translate arch=corei7 and arch=nehelam to - corei7 so that it will be mapped to M_INTEL_COREI7 - as cpu type to cover all M_INTEL_COREI7_XXXs. */ - arg_str = corei7; + if (new_target-x_ix86_isa_flags OPTION_MASK_ISA_AES) + arg_str = westmere; + else + /* We translate arch=corei7 and arch=nehelam to Trivial typo above: arch=nehalem. OK for mainline with these changes. Thanks, Uros.
Re: [Patch, i386] Separate Intel processor with expanded ISA
Updated patch with test.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ccbea0f..e80c30b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2013-12-29 Allan Sandfeld Jensen sandf...@kde.org
+ * config/i386/i386.c (get_builtin_code_for_version): Separate
+ Westmere from Nehalem, Ivy Bridge from Sandy Bridge and
+ Broadwell from Haswell.
+
2014-01-25 Walter Lee w...@tilera.com
* config/tilegx/sync.md (atomic_fetch_sub): Fix negation and
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index cf79486..50f3624 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -31298,18 +31298,27 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
priority = P_PROC_SSSE3;
break;
case PROCESSOR_NEHALEM:
- /* We translate arch=corei7 and arch=nehelam to
- corei7 so that it will be mapped to M_INTEL_COREI7
- as cpu type to cover all M_INTEL_COREI7_XXXs. */
- arg_str = corei7;
+ if (new_target-x_ix86_isa_flags OPTION_MASK_ISA_AES)
+ arg_str = westmere;
+ else
+ /* We translate arch=corei7 and arch=nehelam to
+ corei7 so that it will be mapped to M_INTEL_COREI7
+ as cpu type to cover all M_INTEL_COREI7_XXXs. */
+ arg_str = corei7;
priority = P_PROC_SSE4_2;
break;
case PROCESSOR_SANDYBRIDGE:
- arg_str = sandybridge;
+ if (new_target-x_ix86_isa_flags OPTION_MASK_ISA_F16C)
+ arg_str = ivybridge;
+ else
+ arg_str = sandybridge;
priority = P_PROC_AVX;
break;
case PROCESSOR_HASWELL:
- arg_str = haswell;
+ if (new_target-x_ix86_isa_flags OPTION_MASK_ISA_ADX)
+ arg_str = broadwell;
+ else
+ arg_str = haswell;
priority = P_PROC_AVX2;
break;
case PROCESSOR_BONNELL:
diff --git a/gcc/testsuite/g++.dg/ext/mv16.C b/gcc/testsuite/g++.dg/ext/mv16.C
new file mode 100644
index 000..4737c79
--- /dev/null
+++ b/gcc/testsuite/g++.dg/ext/mv16.C
@@ -0,0 +1,69 @@
+// Test that dispatching can choose the right multiversion
+// for Intel CPUs with the same internal GCC processor id
+// but slighly different sets of x86 extensions.
+
+// { dg-do run { target i?86-*-* x86_64-*-* } }
+// { dg-require-ifunc }
+// { dg-options -O2 }
+
+#include assert.h
+
+int __attribute__ ((target(default)))
+foo ()
+{
+return 0;
+}
+
+int __attribute__ ((target(arch=nehalem)))
+foo ()
+{
+return 4;
+}
+
+int __attribute__ ((target(arch=westmere)))
+foo ()
+{
+return 5;
+}
+
+int __attribute__ ((target(arch=sandybridge)))
+foo ()
+{
+return 8;
+}
+
+int __attribute__ ((target(arch=ivybridge)))
+foo ()
+{
+return 9;
+}
+
+int __attribute__ ((target(arch=haswell)))
+foo ()
+{
+return 12;
+}
+
+int main ()
+{
+int val = foo ();
+
+if (__builtin_cpu_is (nehalem))
+ assert (val == 4);
+else
+if (__builtin_cpu_is (westmere))
+ assert (val == 5);
+else
+if (__builtin_cpu_is (sandybridge))
+ assert (val == 8);
+else
+if (__builtin_cpu_is (ivybridge))
+ assert (val == 9);
+else
+if (__builtin_cpu_is (haswell))
+ assert (val == 12);
+else
+ assert (val == 0);
+
+return 0;
+}
Re: [Patch, i386] Separate Intel processor with expanded ISA
Hello Allan, On 07 Jan 20:54, Allan Sandfeld Jensen wrote: On Sunday 29 December 2013, Allan Sandfeld Jensen wrote: The function dispatcher might currently choose functions declared with target(arch=ivybridge) on a Sandy Bridge CPU. This happens because the function is only detected as sandybridge when generated. This looks like a bug to me. Could you add testcase as well? -- Thanks, K
Re: [Patch, i386] Separate Intel processor with expanded ISA
No comments? On Sunday 29 December 2013, Allan Sandfeld Jensen wrote: The function dispatcher might currently choose functions declared with target(arch=ivybridge) on a Sandy Bridge CPU. This happens because the function is only detected as sandybridge when generated. The attached patch detects Westmere, Ivybridge and Broadwell processors based on new ISAs they support. Regards `Allan
