Re: [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests.

2016-06-08 Thread Christophe Lyon 
On 8 June 2016 at 10:47, Christophe Lyon  wrote:
> On 8 June 2016 at 09:37, Christophe Lyon  wrote:
>> On 7 June 2016 at 19:05, Wilco Dijkstra  wrote:
>>> Hi,
>>>
>>>
>>> These new tests cause failures due to running on non-ARMv8 hardware - the
>>> target check should be arm_v8_neon_hw. Also they don't run on AArch64
>>> hardware as arm_v8_neon_ok/arm_v8_neon_hw isn't true.
>>
>> This really makes sense.
>>
>> I use QEMU to run the tests, and according to my logs, the tests are compiled
>> with -mfpu=neon-fp-armv8 -march=armv8-a
>> and QEMU --cpu cortex-a9 (on the validation configurations intended to
>> validate armv7-a).
>>
>> So... it looks like QEMU failed to reject the invalid instructions?
>> I'm using QEMU-2.4.1.
>>
> Looking in more details, objdump says:
>1074c:   f3fa05a0vrintz.f32  d16, d16
> and qemu -d in_asm says:
> 0x0001074c:  f3fa05a0  vabal.uq8, d26, d16
>
> and I've just had the same behaviour with QEMU-2.6.0
>
> incorrect decoding probably means incorrect execution
> (but how does the test manage to pass?).
>
After running QEMU in debug mode, it just seems that it fails to reject the
instruction, and executes it correctly.
I'm going to file a bug.

Thanks for catching this.

> Christophe
>
>>> check_effective_target_arm_v8_neon_hw in testsuite/lib/target-supports.exp
>>> needs to be extended to allow running on AArch64 as well, as these tests
>>> pass when I remove the dg-require-effective-target line.
>>
>> Probably, I didn't take AArch64 into account when added these.
>> AArch64 intrinsics tests completion is still to be done.
>>
>> Christophe
>>
>>>
>>> Wilco
>>>
>>>
>>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
>>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
>>> new file mode 100644
>>> index 000..5f492d4
>>> --- /dev/null
>>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
>>> @@ -0,0 +1,16 @@
>>> +/* { dg-require-effective-target arm_v8_neon_ok } */
>>>
>>> This should be arm_v8_neon_hw (the arm_v8_neon_ok can only be used for
>>> compilation).
>>>
>>> +/* { dg-add-options arm_v8_neon } */
>>>
>>>

Re: [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests.

2016-06-08 Thread Christophe Lyon 
On 8 June 2016 at 09:37, Christophe Lyon  wrote:
> On 7 June 2016 at 19:05, Wilco Dijkstra  wrote:
>> Hi,
>>
>>
>> These new tests cause failures due to running on non-ARMv8 hardware - the
>> target check should be arm_v8_neon_hw. Also they don't run on AArch64
>> hardware as arm_v8_neon_ok/arm_v8_neon_hw isn't true.
>
> This really makes sense.
>
> I use QEMU to run the tests, and according to my logs, the tests are compiled
> with -mfpu=neon-fp-armv8 -march=armv8-a
> and QEMU --cpu cortex-a9 (on the validation configurations intended to
> validate armv7-a).
>
> So... it looks like QEMU failed to reject the invalid instructions?
> I'm using QEMU-2.4.1.
>
Looking in more details, objdump says:
   1074c:   f3fa05a0vrintz.f32  d16, d16
and qemu -d in_asm says:
0x0001074c:  f3fa05a0  vabal.uq8, d26, d16

and I've just had the same behaviour with QEMU-2.6.0

incorrect decoding probably means incorrect execution
(but how does the test manage to pass?).

Christophe

>> check_effective_target_arm_v8_neon_hw in testsuite/lib/target-supports.exp
>> needs to be extended to allow running on AArch64 as well, as these tests
>> pass when I remove the dg-require-effective-target line.
>
> Probably, I didn't take AArch64 into account when added these.
> AArch64 intrinsics tests completion is still to be done.
>
> Christophe
>
>>
>> Wilco
>>
>>
>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
>> new file mode 100644
>> index 000..5f492d4
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
>> @@ -0,0 +1,16 @@
>> +/* { dg-require-effective-target arm_v8_neon_ok } */
>>
>> This should be arm_v8_neon_hw (the arm_v8_neon_ok can only be used for
>> compilation).
>>
>> +/* { dg-add-options arm_v8_neon } */
>>
>>

Re: [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests.

2016-06-08 Thread Christophe Lyon 
On 7 June 2016 at 19:05, Wilco Dijkstra  wrote:
> Hi,
>
>
> These new tests cause failures due to running on non-ARMv8 hardware - the
> target check should be arm_v8_neon_hw. Also they don't run on AArch64
> hardware as arm_v8_neon_ok/arm_v8_neon_hw isn't true.

This really makes sense.

I use QEMU to run the tests, and according to my logs, the tests are compiled
with -mfpu=neon-fp-armv8 -march=armv8-a
and QEMU --cpu cortex-a9 (on the validation configurations intended to
validate armv7-a).

So... it looks like QEMU failed to reject the invalid instructions?
I'm using QEMU-2.4.1.

> check_effective_target_arm_v8_neon_hw in testsuite/lib/target-supports.exp
> needs to be extended to allow running on AArch64 as well, as these tests
> pass when I remove the dg-require-effective-target line.

Probably, I didn't take AArch64 into account when added these.
AArch64 intrinsics tests completion is still to be done.

Christophe

>
> Wilco
>
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
> new file mode 100644
> index 000..5f492d4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
>
> This should be arm_v8_neon_hw (the arm_v8_neon_ok can only be used for
> compilation).
>
> +/* { dg-add-options arm_v8_neon } */
>
>

Re: [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests.

2016-05-19 Thread Kyrill Tkachov 

Hi Christophe,

On 11/05/16 14:23, Christophe Lyon wrote:

2016-05-02  Christophe Lyon  

* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c: New.
* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc: New.
* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c: New.
* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c: New.
* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c: New.
* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c: New.
* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c: New.


Drop the gcc/testsuite from the ChangeLog entry. Just "* gcc.target/aarch64/..."

Ok with the fixed ChangeLog.

Thanks,
Kyrill



Change-Id: Iab5f98dc4b15f9a2f61b622a9f62b207872f1737

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c 
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
new file mode 100644
index 000..5f492d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
@@ -0,0 +1,16 @@
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-add-options arm_v8_neon } */
+
+#include 
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results.  */
+VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc180, 0xc170 };
+VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc180, 0xc170,
+  0xc160, 0xc150 };
+
+#define INSN vrnd
+#define TEST_MSG "VRND"
+
+#include "vrndX.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc 
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
new file mode 100644
index 000..629240d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
@@ -0,0 +1,43 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1 (NAME)
+
+void FNNAME (INSN) (void)
+{
+  /* vector_res = vrndX (vector), then store the result.  */
+#define TEST_VRND2(INSN, Q, T1, T2, W, N)  \
+  VECT_VAR (vector_res, T1, W, N) =\
+INSN##Q##_##T2##W (VECT_VAR (vector, T1, W, N));   \
+vst1##Q##_##T2##W (VECT_VAR (result, T1, W, N),\
+  VECT_VAR (vector_res, T1, W, N))
+
+  /* Two auxliary macros are necessary to expand INSN.  */
+#define TEST_VRND1(INSN, Q, T1, T2, W, N)  \
+  TEST_VRND2 (INSN, Q, T1, T2, W, N)
+
+#define TEST_VRND(Q, T1, T2, W, N) \
+  TEST_VRND1 (INSN, Q, T1, T2, W, N)
+
+  DECL_VARIABLE (vector, float, 32, 2);
+  DECL_VARIABLE (vector, float, 32, 4);
+
+  DECL_VARIABLE (vector_res, float, 32, 2);
+  DECL_VARIABLE (vector_res, float, 32, 4);
+
+  clean_results ();
+
+  VLOAD (vector, buffer, , float, f, 32, 2);
+  VLOAD (vector, buffer, q, float, f, 32, 4);
+
+  TEST_VRND ( , float, f, 32, 2);
+  TEST_VRND (q, float, f, 32, 4);
+
+  CHECK_FP (TEST_MSG, float, 32, 2, PRIx32, expected, "");
+  CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, "");
+}
+
+int
+main (void)
+{
+  FNNAME (INSN) ();
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c 
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c
new file mode 100644
index 000..816fd28d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c
@@ -0,0 +1,16 @@
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-add-options arm_v8_neon } */
+
+#include 
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results.  */
+VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc180, 0xc170 };
+VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc180, 0xc170,
+  0xc160, 0xc150 };
+
+#define INSN vrnda
+#define TEST_MSG "VRNDA"
+
+#include "vrndX.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c 
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c
new file mode 100644
index 000..029880c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c
@@ -0,0 +1,16 @@
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-add-options arm_v8_neon } */
+
+#include 
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results.  */
+VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc180, 0xc170 };
+VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc180, 0xc170,
+  0xc160, 0xc150 };
+
+#define INSN vrndm
+#define TEST_MSG "VRNDM"
+
+#include "vrndX.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c 
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c
new file mode 100644
index 000..571243c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c
@@ -0,0 +1,16 @@
+/* {

Re: [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests.

2016-05-13 Thread James Greenhalgh 
On Wed, May 11, 2016 at 03:23:59PM +0200, Christophe Lyon wrote:
> 2016-05-02  Christophe Lyon  
> 
>   * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c: New.
>   * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc: New.
>   * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c: New.
>   * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c: New.
>   * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c: New.
>   * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c: New.
>   * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c: New.

This is OK in lines with how we test the other intrinsics in this
directory (we haven't really tried to hit corner cases elsewhere). 

Thanks,
James

> 
> Change-Id: Iab5f98dc4b15f9a2f61b622a9f62b207872f1737
> 
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c 
> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
> new file mode 100644
> index 000..5f492d4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
> +/* { dg-add-options arm_v8_neon } */
> +
> +#include 
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results.  */
> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc180, 0xc170 };
> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc180, 0xc170,
> +0xc160, 0xc150 };
> +
> +#define INSN vrnd
> +#define TEST_MSG "VRND"
> +
> +#include "vrndX.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc 
> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
> new file mode 100644
> index 000..629240d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
> @@ -0,0 +1,43 @@
> +#define FNNAME1(NAME) exec_ ## NAME
> +#define FNNAME(NAME) FNNAME1 (NAME)
> +
> +void FNNAME (INSN) (void)
> +{
> +  /* vector_res = vrndX (vector), then store the result.  */
> +#define TEST_VRND2(INSN, Q, T1, T2, W, N)\
> +  VECT_VAR (vector_res, T1, W, N) =  \
> +INSN##Q##_##T2##W (VECT_VAR (vector, T1, W, N)); \
> +vst1##Q##_##T2##W (VECT_VAR (result, T1, W, N),  \
> +VECT_VAR (vector_res, T1, W, N))
> +
> +  /* Two auxliary macros are necessary to expand INSN.  */
> +#define TEST_VRND1(INSN, Q, T1, T2, W, N)\
> +  TEST_VRND2 (INSN, Q, T1, T2, W, N)
> +
> +#define TEST_VRND(Q, T1, T2, W, N)   \
> +  TEST_VRND1 (INSN, Q, T1, T2, W, N)
> +
> +  DECL_VARIABLE (vector, float, 32, 2);
> +  DECL_VARIABLE (vector, float, 32, 4);
> +
> +  DECL_VARIABLE (vector_res, float, 32, 2);
> +  DECL_VARIABLE (vector_res, float, 32, 4);
> +
> +  clean_results ();
> +
> +  VLOAD (vector, buffer, , float, f, 32, 2);
> +  VLOAD (vector, buffer, q, float, f, 32, 4);
> +
> +  TEST_VRND ( , float, f, 32, 2);
> +  TEST_VRND (q, float, f, 32, 4);
> +
> +  CHECK_FP (TEST_MSG, float, 32, 2, PRIx32, expected, "");
> +  CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, "");
> +}
> +
> +int
> +main (void)
> +{
> +  FNNAME (INSN) ();
> +  return 0;
> +}
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c 
> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c
> new file mode 100644
> index 000..816fd28d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
> +/* { dg-add-options arm_v8_neon } */
> +
> +#include 
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results.  */
> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc180, 0xc170 };
> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc180, 0xc170,
> +0xc160, 0xc150 };
> +
> +#define INSN vrnda
> +#define TEST_MSG "VRNDA"
> +
> +#include "vrndX.inc"
> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c 
> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c
> new file mode 100644
> index 000..029880c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c
> @@ -0,0 +1,16 @@
> +/* { dg-require-effective-target arm_v8_neon_ok } */
> +/* { dg-add-options arm_v8_neon } */
> +
> +#include 
> +#include "arm-neon-ref.h"
> +#include "compute-ref-data.h"
> +
> +/* Expected results.  */
> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc180, 0xc170 };
> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc180, 0xc170,
> +0xc160, 0xc150 };
> +
> +#define INSN vrndm
> +#define TEST_MSG "VRNDM"
> +
> +#include "vrndX.inc"
> diff --git

Re: [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests.

2016-05-13 Thread Jiong Wang 



On 12/05/16 13:56, Christophe Lyon wrote:

On 12 May 2016 at 10:45, Jiong Wang  wrote:


On 11/05/16 14:23, Christophe Lyon wrote:

2016-05-02  Christophe Lyon  

 * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c: New.
 * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc:
New.
 * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c:
New.
 * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c:
New.
 * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c:
New.
 * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c:
New.
 * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c:
New.

Change-Id: Iab5f98dc4b15f9a2f61b622a9f62b207872f1737

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
new file mode 100644
index 000..5f492d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
@@ -0,0 +1,16 @@
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-add-options arm_v8_neon } */
+
+#include 
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results.  */
+VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc180, 0xc170 };
+VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc180, 0xc170,
+  0xc160, 0xc150 };
+
+#define INSN vrnd
+#define TEST_MSG "VRND"
+
+#include "vrndX.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
new file mode 100644
index 000..629240d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
@@ -0,0 +1,43 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1 (NAME)
+
+void FNNAME (INSN) (void)
+{
+  /* vector_res = vrndX (vector), then store the result.  */
+#define TEST_VRND2(INSN, Q, T1, T2, W, N)  \
+  VECT_VAR (vector_res, T1, W, N) =\
+INSN##Q##_##T2##W (VECT_VAR (vector, T1, W, N));   \
+vst1##Q##_##T2##W (VECT_VAR (result, T1, W, N),\
+  VECT_VAR (vector_res, T1, W, N))
+
+  /* Two auxliary macros are necessary to expand INSN.  */
+#define TEST_VRND1(INSN, Q, T1, T2, W, N)  \
+  TEST_VRND2 (INSN, Q, T1, T2, W, N)
+
+#define TEST_VRND(Q, T1, T2, W, N) \
+  TEST_VRND1 (INSN, Q, T1, T2, W, N)
+
+  DECL_VARIABLE (vector, float, 32, 2);
+  DECL_VARIABLE (vector, float, 32, 4);
+
+  DECL_VARIABLE (vector_res, float, 32, 2);
+  DECL_VARIABLE (vector_res, float, 32, 4);
+
+  clean_results ();
+
+  VLOAD (vector, buffer, , float, f, 32, 2);
+  VLOAD (vector, buffer, q, float, f, 32, 4);
+
+  TEST_VRND ( , float, f, 32, 2);
+  TEST_VRND (q, float, f, 32, 4);
+
+  CHECK_FP (TEST_MSG, float, 32, 2, PRIx32, expected, "");
+  CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, "");
+}
+
+int
+main (void)
+{
+  FNNAME (INSN) ();
+  return 0;
+}


Hi Christophe,

   I have a question on how test inputs are selected?

   For example vrndm is round to integral, towards minus infinity while vrnda
is to nearest with ties to even, has these differences been tested?


Hi Jiong,

For this particular case, no, I didn't specifically chose input values to check
these differences.

This can be done as a follow-up?


I think it's fine as this patch series itself is anyway a step forward 
on making sure all intrinsics are tested.


Thanks.

Regards,
Jiong

Re: [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests.

2016-05-12 Thread Christophe Lyon 
On 12 May 2016 at 10:45, Jiong Wang  wrote:
>
>
> On 11/05/16 14:23, Christophe Lyon wrote:
>>
>> 2016-05-02  Christophe Lyon  
>>
>> * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c: New.
>> * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc:
>> New.
>> * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c:
>> New.
>> * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c:
>> New.
>> * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c:
>> New.
>> * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c:
>> New.
>> * gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c:
>> New.
>>
>> Change-Id: Iab5f98dc4b15f9a2f61b622a9f62b207872f1737
>>
>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
>> new file mode 100644
>> index 000..5f492d4
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
>> @@ -0,0 +1,16 @@
>> +/* { dg-require-effective-target arm_v8_neon_ok } */
>> +/* { dg-add-options arm_v8_neon } */
>> +
>> +#include 
>> +#include "arm-neon-ref.h"
>> +#include "compute-ref-data.h"
>> +
>> +/* Expected results.  */
>> +VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc180, 0xc170 };
>> +VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc180, 0xc170,
>> +  0xc160, 0xc150 };
>> +
>> +#define INSN vrnd
>> +#define TEST_MSG "VRND"
>> +
>> +#include "vrndX.inc"
>> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
>> new file mode 100644
>> index 000..629240d
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
>> @@ -0,0 +1,43 @@
>> +#define FNNAME1(NAME) exec_ ## NAME
>> +#define FNNAME(NAME) FNNAME1 (NAME)
>> +
>> +void FNNAME (INSN) (void)
>> +{
>> +  /* vector_res = vrndX (vector), then store the result.  */
>> +#define TEST_VRND2(INSN, Q, T1, T2, W, N)  \
>> +  VECT_VAR (vector_res, T1, W, N) =\
>> +INSN##Q##_##T2##W (VECT_VAR (vector, T1, W, N));   \
>> +vst1##Q##_##T2##W (VECT_VAR (result, T1, W, N),\
>> +  VECT_VAR (vector_res, T1, W, N))
>> +
>> +  /* Two auxliary macros are necessary to expand INSN.  */
>> +#define TEST_VRND1(INSN, Q, T1, T2, W, N)  \
>> +  TEST_VRND2 (INSN, Q, T1, T2, W, N)
>> +
>> +#define TEST_VRND(Q, T1, T2, W, N) \
>> +  TEST_VRND1 (INSN, Q, T1, T2, W, N)
>> +
>> +  DECL_VARIABLE (vector, float, 32, 2);
>> +  DECL_VARIABLE (vector, float, 32, 4);
>> +
>> +  DECL_VARIABLE (vector_res, float, 32, 2);
>> +  DECL_VARIABLE (vector_res, float, 32, 4);
>> +
>> +  clean_results ();
>> +
>> +  VLOAD (vector, buffer, , float, f, 32, 2);
>> +  VLOAD (vector, buffer, q, float, f, 32, 4);
>> +
>> +  TEST_VRND ( , float, f, 32, 2);
>> +  TEST_VRND (q, float, f, 32, 4);
>> +
>> +  CHECK_FP (TEST_MSG, float, 32, 2, PRIx32, expected, "");
>> +  CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, "");
>> +}
>> +
>> +int
>> +main (void)
>> +{
>> +  FNNAME (INSN) ();
>> +  return 0;
>> +}
>>
>
> Hi Christophe,
>
>   I have a question on how test inputs are selected?
>
>   For example vrndm is round to integral, towards minus infinity while vrnda
> is to nearest with ties to even, has these differences been tested?
>

Hi Jiong,

For this particular case, no, I didn't specifically chose input values to check
these differences.

This can be done as a follow-up?

Thanks,

Christophe

>   Thanks.
>
> Regards,
> Jiong

Re: [Patch ARM/AArch64 09/11] Add missing vrnd{,a,m,n,p,x} tests.

2016-05-12 Thread Jiong Wang 



On 11/05/16 14:23, Christophe Lyon wrote:

2016-05-02  Christophe Lyon  

* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c: New.
* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc: New.
* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnda.c: New.
* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndm.c: New.
* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndn.c: New.
* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndp.c: New.
* gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndx.c: New.

Change-Id: Iab5f98dc4b15f9a2f61b622a9f62b207872f1737

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c 
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
new file mode 100644
index 000..5f492d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrnd.c
@@ -0,0 +1,16 @@
+/* { dg-require-effective-target arm_v8_neon_ok } */
+/* { dg-add-options arm_v8_neon } */
+
+#include 
+#include "arm-neon-ref.h"
+#include "compute-ref-data.h"
+
+/* Expected results.  */
+VECT_VAR_DECL (expected, hfloat, 32, 2) [] = { 0xc180, 0xc170 };
+VECT_VAR_DECL (expected, hfloat, 32, 4) [] = { 0xc180, 0xc170,
+  0xc160, 0xc150 };
+
+#define INSN vrnd
+#define TEST_MSG "VRND"
+
+#include "vrndX.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc 
b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
new file mode 100644
index 000..629240d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndX.inc
@@ -0,0 +1,43 @@
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1 (NAME)
+
+void FNNAME (INSN) (void)
+{
+  /* vector_res = vrndX (vector), then store the result.  */
+#define TEST_VRND2(INSN, Q, T1, T2, W, N)  \
+  VECT_VAR (vector_res, T1, W, N) =\
+INSN##Q##_##T2##W (VECT_VAR (vector, T1, W, N));   \
+vst1##Q##_##T2##W (VECT_VAR (result, T1, W, N),\
+  VECT_VAR (vector_res, T1, W, N))
+
+  /* Two auxliary macros are necessary to expand INSN.  */
+#define TEST_VRND1(INSN, Q, T1, T2, W, N)  \
+  TEST_VRND2 (INSN, Q, T1, T2, W, N)
+
+#define TEST_VRND(Q, T1, T2, W, N) \
+  TEST_VRND1 (INSN, Q, T1, T2, W, N)
+
+  DECL_VARIABLE (vector, float, 32, 2);
+  DECL_VARIABLE (vector, float, 32, 4);
+
+  DECL_VARIABLE (vector_res, float, 32, 2);
+  DECL_VARIABLE (vector_res, float, 32, 4);
+
+  clean_results ();
+
+  VLOAD (vector, buffer, , float, f, 32, 2);
+  VLOAD (vector, buffer, q, float, f, 32, 4);
+
+  TEST_VRND ( , float, f, 32, 2);
+  TEST_VRND (q, float, f, 32, 4);
+
+  CHECK_FP (TEST_MSG, float, 32, 2, PRIx32, expected, "");
+  CHECK_FP (TEST_MSG, float, 32, 4, PRIx32, expected, "");
+}
+
+int
+main (void)
+{
+  FNNAME (INSN) ();
+  return 0;
+}



Hi Christophe,

  I have a question on how test inputs are selected?

  For example vrndm is round to integral, towards minus infinity while 
vrnda is to nearest with ties to even, has these differences been tested?


  Thanks.

Regards,
Jiong