Re: Repost [PATCH 4/6] PowerPC: Make MMA insns support DMR registers.
On Sun, Feb 04, 2024 at 11:21:49AM +0800, Kewen.Lin wrote:
> Hi Mike,
>
> > --- a/gcc/config/rs6000/mma.md
> > +++ b/gcc/config/rs6000/mma.md
> > @@ -559,190 +559,249 @@ (define_insn "*mma_disassemble_acc_dm"
> >"dmxxextfdmr256 %0,%1,2"
> >[(set_attr "type" "mma")])
> >
> > -(define_insn "mma_"
> > +;; MMA instructions that do not use their accumulators as an input, still
> > must
> > +;; not allow their vector operands to overlap the registers used by the
> > +;; accumulator. We enforce this by marking the output as early clobber.
> > If we
> > +;; have dense math, we don't need the whole prime/de-prime action, so just
> > make
> > +;; thse instructions be NOPs.
>
> typo: thse.
Ok.
> > +
> > +(define_expand "mma_"
> > + [(set (match_operand:XO 0 "register_operand")
> > + (unspec:XO [(match_operand:XO 1 "register_operand")]
>
> s/register_operand/accumulator_operand/?
Ok.
> > + MMA_ACC))]
> > + "TARGET_MMA"
> > +{
> > + if (TARGET_DENSE_MATH)
> > +{
> > + if (!rtx_equal_p (operands[0], operands[1]))
> > + emit_move_insn (operands[0], operands[1]);
> > + DONE;
> > +}
> > +
> > + /* Generate the prime/de-prime code. */
> > +})
> > +
> > +(define_insn "*mma_"
>
> May be better to name with "*mma__nodm"?
Ok.
> >[(set (match_operand:XO 0 "fpr_reg_operand" "=")
> > (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0")]
> > MMA_ACC))]
> > - "TARGET_MMA"
> > + "TARGET_MMA && !TARGET_DENSE_MATH"
>
> I found that "TARGET_MMA && !TARGET_DENSE_MATH" is used much (like changes in
> function
> rs6000_split_multireg_move in this patch and some places in previous
> patches), maybe we
> can introduce a macro named as TARGET_MMA_NODM short for it?
As I said in the message about the last patch, I added
TARGET_MMA_NO_DENSE_MATH.
> >" %A0"
> >[(set_attr "type" "mma")])
> >
> > ;; We can't have integer constants in XOmode so we wrap this in an
> > -;; UNSPEC_VOLATILE.
> > +;; UNSPEC_VOLATILE for the non-dense math case. For dense math, we don't
> > need
> > +;; to disable optimization and we can do a normal UNSPEC.
> >
> > -(define_insn "mma_xxsetaccz"
> > - [(set (match_operand:XO 0 "fpr_reg_operand" "=d")
> > +(define_expand "mma_xxsetaccz"
> > + [(set (match_operand:XO 0 "register_operand")
>
> s/register_operand/accumulator_operand/?
Ok.
> > (unspec_volatile:XO [(const_int 0)]
> > UNSPECV_MMA_XXSETACCZ))]
> >"TARGET_MMA"
> > +{
> > + if (TARGET_DENSE_MATH)
> > +{
> > + emit_insn (gen_mma_xxsetaccz_dm (operands[0]));
> > + DONE;
> > +}
> > +})
> > +
> > +(define_insn "*mma_xxsetaccz_vsx"
>
> s/vsx/nodm/
Ok.
> > + [(set (match_operand:XO 0 "fpr_reg_operand" "=d")
> > + (unspec_volatile:XO [(const_int 0)]
> > + UNSPECV_MMA_XXSETACCZ))]
> > + "TARGET_MMA && !TARGET_DENSE_MATH"
> >"xxsetaccz %A0"
> >[(set_attr "type" "mma")])
> >
> > +
> > +(define_insn "mma_xxsetaccz_dm"
> > + [(set (match_operand:XO 0 "dmr_operand" "=wD")
> > + (unspec:XO [(const_int 0)]
> > + UNSPECV_MMA_XXSETACCZ))]
> > + "TARGET_DENSE_MATH"
> > + "dmsetdmrz %0"
> > + [(set_attr "type" "mma")])
> > +
> > (define_insn "mma_"
> > - [(set (match_operand:XO 0 "fpr_reg_operand" "=,")
> > - (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
> > - (match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
> > + [(set (match_operand:XO 0 "accumulator_operand" "=wD,,")
> > + (unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "wa,v,?wa")
> > + (match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")]
> > MMA_VV))]
> >"TARGET_MMA"
> >" %A0,%x1,%x2"
> > - [(set_attr "type" "mma")])
> > + [(set_attr "type" "mma")
> > + (set_attr "isa" "dm,not_dm,not_dm")])
>
> Like what's suggested in previous patches, s/not_dm/nodm/
Ok.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
Re: Repost [PATCH 4/6] PowerPC: Make MMA insns support DMR registers.
Hi Mike,
on 2024/1/6 07:39, Michael Meissner wrote:
> This patch changes the MMA instructions to use either FPR registers
> (-mcpu=power10) or DMRs (-mcpu=future). In this patch, the existing MMA
> instruction names are used.
>
> A macro (__PPC_DMR__) is defined if the MMA instructions use the DMRs.
>
> The patches have been tested on both little and big endian systems. Can I
> check
> it into the master branch?
>
> 2024-01-05 Michael Meissner
>
> gcc/
>
> * config/rs6000/mma.md (mma_): New define_expand to handle
> mma_ for dense math and non dense math.
> (mma_ insn): Restrict to non dense math.
> (mma_xxsetaccz): Convert to define_expand to handle non dense math and
> dense math.
> (mma_xxsetaccz_vsx): Rename from mma_xxsetaccz and restrict usage to non
> dense math.
> (mma_xxsetaccz_dm): Dense math version of mma_xxsetaccz.
> (mma_): Add support for dense math.
> (mma_): Likewise.
> (mma_): Likewise.
> (mma_): Likewise.
> (mma_): Likewise.
> (mma_): Likewise.
> (mma_): Likewise.
> (mma_): Likewise.
> (mma_): Likewise.
> (mma_): Likewise.
> (mma_): Likewise.
> (mma_): Likewise.
> (mma_): Likewise.
> (mma_): Likewise.
> * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
> __PPC_DMR__ if we have dense math instructions.
> * config/rs6000/rs6000.cc (print_operand): Make %A handle only DMRs if
> dense math and only FPRs if not dense math.
> (rs6000_split_multireg_move): Do not generate the xxmtacc instruction to
> prime the DMR registers or the xxmfacc instruction to de-prime
> instructions if we have dense math register support.
> ---
> gcc/config/rs6000/mma.md | 247 +-
> gcc/config/rs6000/rs6000-c.cc | 3 +
> gcc/config/rs6000/rs6000.cc | 35 ++---
> 3 files changed, 176 insertions(+), 109 deletions(-)
>
> diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
> index bb898919ab5..525a85146ff 100644
> --- a/gcc/config/rs6000/mma.md
> +++ b/gcc/config/rs6000/mma.md
> @@ -559,190 +559,249 @@ (define_insn "*mma_disassemble_acc_dm"
>"dmxxextfdmr256 %0,%1,2"
>[(set_attr "type" "mma")])
>
> -(define_insn "mma_"
> +;; MMA instructions that do not use their accumulators as an input, still
> must
> +;; not allow their vector operands to overlap the registers used by the
> +;; accumulator. We enforce this by marking the output as early clobber. If
> we
> +;; have dense math, we don't need the whole prime/de-prime action, so just
> make
> +;; thse instructions be NOPs.
typo: thse.
> +
> +(define_expand "mma_"
> + [(set (match_operand:XO 0 "register_operand")
> + (unspec:XO [(match_operand:XO 1 "register_operand")]
s/register_operand/accumulator_operand/?
> +MMA_ACC))]
> + "TARGET_MMA"
> +{
> + if (TARGET_DENSE_MATH)
> +{
> + if (!rtx_equal_p (operands[0], operands[1]))
> + emit_move_insn (operands[0], operands[1]);
> + DONE;
> +}
> +
> + /* Generate the prime/de-prime code. */
> +})
> +
> +(define_insn "*mma_"
May be better to name with "*mma__nodm"?
>[(set (match_operand:XO 0 "fpr_reg_operand" "=")
> (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0")]
> MMA_ACC))]
> - "TARGET_MMA"
> + "TARGET_MMA && !TARGET_DENSE_MATH"
I found that "TARGET_MMA && !TARGET_DENSE_MATH" is used much (like changes in
function
rs6000_split_multireg_move in this patch and some places in previous patches),
maybe we
can introduce a macro named as TARGET_MMA_NODM short for it?
>" %A0"
>[(set_attr "type" "mma")])
>
> ;; We can't have integer constants in XOmode so we wrap this in an
> -;; UNSPEC_VOLATILE.
> +;; UNSPEC_VOLATILE for the non-dense math case. For dense math, we don't
> need
> +;; to disable optimization and we can do a normal UNSPEC.
>
> -(define_insn "mma_xxsetaccz"
> - [(set (match_operand:XO 0 "fpr_reg_operand" "=d")
> +(define_expand "mma_xxsetaccz"
> + [(set (match_operand:XO 0 "register_operand")
s/register_operand/accumulator_operand/?
> (unspec_volatile:XO [(const_int 0)]
> UNSPECV_MMA_XXSETACCZ))]
>"TARGET_MMA"
> +{
> + if (TARGET_DENSE_MATH)
> +{
> + emit_insn (gen_mma_xxsetaccz_dm (operands[0]));
> + DONE;
> +}
> +})
> +
> +(define_insn "*mma_xxsetaccz_vsx"
s/vsx/nodm/
> + [(set (match_operand:XO 0 "fpr_reg_operand" "=d")
> + (unspec_volatile:XO [(const_int 0)]
> + UNSPECV_MMA_XXSETACCZ))]
> + "TARGET_MMA && !TARGET_DENSE_MATH"
>"xxsetaccz %A0"
>[(set_attr "type" "mma")])
>
> +
> +(define_insn "mma_xxsetaccz_dm"
> + [(set (match_operand:XO 0 "dmr_operand" "=wD")
> + (unspec:XO [(const_int 0)]
> +UNSPECV_MMA_XXSETACCZ))]
> + "TARGET_DENSE_MATH"
> + "dmsetdmrz %0"
> + [(set_attr "type" "mma")])
> +
> (define_insn "mma_"
> -
