from:"wangf...@eswincomputing.com"

Re: Re: [PATCH 2/3] RISC-V: Add Zvfbfmin and Zvfbfwma intrinsic

2024-06-26 Thread wangf...@eswincomputing.com

On 2024-06-22 00:16  Patrick O'Neill  wrote:
>
>Hi Feng,
>
>Pre-commit has flagged a build-failure for patch 2/3:
>https://github.com/ewlu/gcc-precommit-ci/issues/1786#issuecomment-2181962244
>
>When applied to 9a76db24e04 i386: Allow all register_operand SUBREGs in
>x86_ternlog_idx.
>
>Re-confirmed locally with 5320bcbd342 xstormy16: Fix
>xs_hi_nonmemory_operand.
>
>Additionally there is an apply failure for patch 3/3.
> 
Sorry for the late reply. This is the reason why build failure failed,  the 
patch 2/3 depends on patch 3/3. Do you know the reason
"Failed to merge in the changes."? Do I need rebase the patch 3/3? Thanks.
>Results can be seen here:
>Series:
>https://patchwork.sourceware.org/project/gcc/list/?series=35407
>Patch 2/3:
>https://patchwork.sourceware.org/project/gcc/patch/20240621015459.13525-2-wangf...@eswincomputing.com/
>https://github.com/ewlu/gcc-precommit-ci/issues/1786#issuecomment-2181863112
>Patch 3/3:
>https://patchwork.sourceware.org/project/gcc/patch/20240621015459.13525-3-wangf...@eswincomputing.com/
>https://github.com/ewlu/gcc-precommit-ci/issues/1784#issuecomment-2181861381
>
>Thanks,
>Patrick
>
>On 6/20/24 18:54, Feng Wang wrote:
>> Accroding to the intrinsic doc, the 'Zvfbfmin' and 'Zvfbfwma' intrinsic
>> functions are added by this patch.
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv-vector-builtins-bases.cc (class vfncvtbf16_f):
>>     Add 'Zvfbfmin' intrinsic in bases.
>> (class vfwcvtbf16_f): Ditto.
>> (class vfwmaccbf16): Add 'Zvfbfwma' intrinsic in bases.
>> (BASE): Add BASE macro for 'Zvfbfmin' and 'Zvfbfwma'.
>> * config/riscv/riscv-vector-builtins-bases.h: Add declaration for 'Zvfbfmin' 
>> and 'Zvfbfwma'.
>> * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
>>     Add builtins def for 'Zvfbfmin' and 'Zvfbfwma'.
>> (vfncvtbf16_f): Ditto.
>> (vfncvtbf16_f_frm): Ditto.
>> (vfwcvtbf16_f): Ditto.
>> (vfwmaccbf16): Ditto.
>> (vfwmaccbf16_frm): Ditto.
>> * config/riscv/riscv-vector-builtins-shapes.cc (supports_vectype_p):
>>     Add vector intrinsic build judgment for BFloat16.
>> (build_all): Ditto.
>> (BASE_NAME_MAX_LEN): Adjust max length.
>> * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_F32_OPS):
>>     Add new operand type for BFloat16.
>> (vfloat32mf2_t): Ditto.
>> (vfloat32m1_t): Ditto.
>> (vfloat32m2_t): Ditto.
>> (vfloat32m4_t): Ditto.
>> (vfloat32m8_t): Ditto.
>> * config/riscv/riscv-vector-builtins.cc (DEF_RVV_F32_OPS): Ditto.
>> (validate_instance_type_required_extensions):
>>     Add required_ext checking for 'Zvfbfmin' and 'Zvfbfwma'.
>> * config/riscv/riscv-vector-builtins.h (enum required_ext):
>>     Add required_ext declaration for 'Zvfbfmin' and 'Zvfbfwma'.
>> (reqired_ext_to_isa_name): Ditto.
>> (required_extensions_specified): Ditto.
>> (struct function_group_info): Add match case for 'Zvfbfmin' and 'Zvfbfwma'.
>> * config/riscv/riscv.cc (riscv_validate_vector_type):
>>     Add required_ext checking for 'Zvfbfmin' and 'Zvfbfwma'.
>>
>> ---

Re: Re: [PATCH 2/3] RISC-V: Add Zvfbfmin and Zvfbfwma intrinsic

2024-06-26 Thread wangf...@eswincomputing.com

On 2024-06-27 08:52  wangfeng  wrote: 
I rebased the patch 3/3, there is a conflict. I will submit again after 
internal code review. 
Due to many changes, the patch was split, so a dependency relationship between 
patch 2/3
and patch 3/3 was generated. Could you help pull both patches down when run the 
regression
test after I submit the v2 version?
Thanks.
>
>On 2024-06-22 00:16  Patrick O'Neill  wrote:
>>
>>Hi Feng,
>>
>>Pre-commit has flagged a build-failure for patch 2/3:
>>https://github.com/ewlu/gcc-precommit-ci/issues/1786#issuecomment-2181962244
>>
>>When applied to 9a76db24e04 i386: Allow all register_operand SUBREGs in
>>x86_ternlog_idx.
>>
>>Re-confirmed locally with 5320bcbd342 xstormy16: Fix
>>xs_hi_nonmemory_operand.
>>
>>Additionally there is an apply failure for patch 3/3.
>>
>Sorry for the late reply. This is the reason why build failure failed,  the 
>patch 2/3 depends on patch 3/3. Do you know the reason
>"Failed to merge in the changes."? Do I need rebase the patch 3/3? Thanks.
>>Results can be seen here:
>>Series:
>>https://patchwork.sourceware.org/project/gcc/list/?series=35407
>>Patch 2/3:
>>https://patchwork.sourceware.org/project/gcc/patch/20240621015459.13525-2-wangf...@eswincomputing.com/
>>https://github.com/ewlu/gcc-precommit-ci/issues/1786#issuecomment-2181863112
>>Patch 3/3:
>>https://patchwork.sourceware.org/project/gcc/patch/20240621015459.13525-3-wangf...@eswincomputing.com/
>>https://github.com/ewlu/gcc-precommit-ci/issues/1784#issuecomment-2181861381
>>
>>Thanks,
>>Patrick
>>
>>On 6/20/24 18:54, Feng Wang wrote:
>>> Accroding to the intrinsic doc, the 'Zvfbfmin' and 'Zvfbfwma' intrinsic
>>> functions are added by this patch.
>>>
>>> gcc/ChangeLog:
>>>
>>> * config/riscv/riscv-vector-builtins-bases.cc (class vfncvtbf16_f):
>>>     Add 'Zvfbfmin' intrinsic in bases.
>>> (class vfwcvtbf16_f): Ditto.
>>> (class vfwmaccbf16): Add 'Zvfbfwma' intrinsic in bases.
>>> (BASE): Add BASE macro for 'Zvfbfmin' and 'Zvfbfwma'.
>>> * config/riscv/riscv-vector-builtins-bases.h: Add declaration for 
>>> 'Zvfbfmin' and 'Zvfbfwma'.
>>> * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
>>>     Add builtins def for 'Zvfbfmin' and 'Zvfbfwma'.
>>> (vfncvtbf16_f): Ditto.
>>> (vfncvtbf16_f_frm): Ditto.
>>> (vfwcvtbf16_f): Ditto.
>>> (vfwmaccbf16): Ditto.
>>> (vfwmaccbf16_frm): Ditto.
>>> * config/riscv/riscv-vector-builtins-shapes.cc (supports_vectype_p):
>>>     Add vector intrinsic build judgment for BFloat16.
>>> (build_all): Ditto.
>>> (BASE_NAME_MAX_LEN): Adjust max length.
>>> * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_F32_OPS):
>>>     Add new operand type for BFloat16.
>>> (vfloat32mf2_t): Ditto.
>>> (vfloat32m1_t): Ditto.
>>> (vfloat32m2_t): Ditto.
>>> (vfloat32m4_t): Ditto.
>>> (vfloat32m8_t): Ditto.
>>> * config/riscv/riscv-vector-builtins.cc (DEF_RVV_F32_OPS): Ditto.
>>> (validate_instance_type_required_extensions):
>>>     Add required_ext checking for 'Zvfbfmin' and 'Zvfbfwma'.
>>> * config/riscv/riscv-vector-builtins.h (enum required_ext):
>>>     Add required_ext declaration for 'Zvfbfmin' and 'Zvfbfwma'.
>>> (reqired_ext_to_isa_name): Ditto.
>>> (required_extensions_specified): Ditto.
>>> (struct function_group_info): Add match case for 'Zvfbfmin' and 'Zvfbfwma'.
>>> * config/riscv/riscv.cc (riscv_validate_vector_type):
>>>     Add required_ext checking for 'Zvfbfmin' and 'Zvfbfwma'.
>>>
>>> ---

Re: Re: [PATCH 3/3 v3] RISC-V: Add md files for vector BFloat16

2024-07-14 Thread wangf...@eswincomputing.com

On 2024-07-12 06:19  Jeff Law  wrote:
>
>
>
>On 7/11/24 1:10 AM, Feng Wang wrote:
>> V3: Add Bfloat16 vector insn in generic-vector-ooo.md
>> v2: Rebase
>> Accroding to the BFloat16 spec, some vector iterators and new pattern
>> are added in md files.
>>
>> Signed-off-by: Feng Wang 
>> gcc/ChangeLog:
>>
>> * config/riscv/generic-vector-ooo.md: Add def_insn_reservation for vector 
>> BFloat16.
>> * config/riscv/riscv.md: Add new insn name for vector BFloat16.
>> * config/riscv/vector-iterators.md: Add some iterators for vector BFloat16.
>> * config/riscv/vector.md: Add some attribute for vector BFloat16.
>> * config/riscv/vector-bfloat16.md: New file. Add insn pattern vector 
>> BFloat16.
>Note the spaces vs tabs issue pointed out by the lint phase.  Those
>should be fixed.  I don't think the rest of the lint issues need to be
>fixed. 
>jeff
Thanks, will fix this lint error type according to the CI log and then commit 
it.

Re: Re: [RE] [v2] RISC-V: Add Zfbfmin extension

2024-06-18 Thread wangf...@eswincomputing.com

Hi Jin,

Will submit patch after internal review，maybe today.

wangf...@eswincomputing.com

From: Jin Ma
Date: 2024-06-18 18:25
To: wangfeng
CC: Kito Cheng; juzhe.zhong; jinma.contrib; zengxiao; gcc-patches; Fei Gao
Subject: Re: [RE] [v2] RISC-V: Add Zfbfmin extension

Hi, Feng
  Any new developments here on zvfbfmin and zvfbfwma?

BR,
Jin

--
From:Fei Gao 
Send Time:2024 Jun. 7 (Fri.) 17:34
To:jinma; "gcc-patches"; 
zengxiao; wangfeng
Cc:jeffreyalaw; Kito Cheng; 
"juzhe.zhong"; "jinma.contrib"; 
jinma
Subject:Re: [RE] [v2] RISC-V: Add Zfbfmin extension

Hi Jin

We have completed zvfbfmin and zvfbfwma in GCC. 
Wang Feng will post after dragon boat festival. 

BR, 
Fei
From: Jin Ma
Date: 2024-06-07 15:35
To: gcc-patches; zengxiao
CC: jeffreyalaw; kito.cheng; juzhe.zhong; jinma.contrib; Jin Ma
Subject: [RE] [v2] RISC-V: Add Zfbfmin extension

Hi,
Is there a plan to implement zvfbfmin and zvfbfwma? Or how can I get the 
relevant patches
in advance for testing? By the way, The LLVM seems to be fully implemented now 
:-)

Ref:

https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/293

https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/main/auto-generated/bfloat16/intrinsic_funcs.adoc

Thanks,
Jin

Re: Re: [PATCH 2/3] RISC-V: Add Zvfbfmin and Zvfbfwma intrinsic

2024-06-21 Thread wangf...@eswincomputing.com

On 2024-06-21 12:24  juzhe.zhong  wrote:
>
>+  if (*group.shape == shapes::loadstore
>+  || *group.shape == shapes::indexed_loadstore
>+  || *group.shape == shapes::vundefined
>+  || *group.shape == shapes::misc
>+  || *group.shape == shapes::vset
>+  || *group.shape == shapes::vget
>+  || *group.shape == shapes::vcreate
>+  || *group.shape == shapes::fault_load
>+  || *group.shape == shapes::seg_loadstore
>+  || *group.shape == shapes::seg_indexed_loadstore
>+  || *group.shape == shapes::seg_fault_load)
>+    return true;
>
>I prefer use swith-case:
>
>switch
>case...
>return true
>default
>return fasle;
>
>
>juzhe.zh...@rivai.ai
> 

I tried your suggestion, but this type(function_shape) can't use switch case 
structure. It will require adding more code if using it.
If you have a beteer method, please don't hesitate to share it.
Thanks.

>From: Feng Wang
>Date: 2024-06-21 09:54
>To: gcc-patches
>CC: kito.cheng; juzhe.zhong; jinma.contrib; Feng Wang
>Subject: [PATCH 2/3] RISC-V: Add Zvfbfmin and Zvfbfwma intrinsic
>Accroding to the intrinsic doc, the 'Zvfbfmin' and 'Zvfbfwma' intrinsic
>functions are added by this patch.
>
>gcc/ChangeLog:
>
>* config/riscv/riscv-vector-builtins-bases.cc (class vfncvtbf16_f):
>    Add 'Zvfbfmin' intrinsic in bases.
>(class vfwcvtbf16_f): Ditto.
>(class vfwmaccbf16): Add 'Zvfbfwma' intrinsic in bases.
>(BASE): Add BASE macro for 'Zvfbfmin' and 'Zvfbfwma'.
>* config/riscv/riscv-vector-builtins-bases.h: Add declaration for 'Zvfbfmin' 
>and 'Zvfbfwma'.
>* config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
>    Add builtins def for 'Zvfbfmin' and 'Zvfbfwma'.
>(vfncvtbf16_f): Ditto.
>(vfncvtbf16_f_frm): Ditto.
>(vfwcvtbf16_f): Ditto.
>(vfwmaccbf16): Ditto.
>(vfwmaccbf16_frm): Ditto.
>* config/riscv/riscv-vector-builtins-shapes.cc (supports_vectype_p):
>    Add vector intrinsic build judgment for BFloat16.
>(build_all): Ditto.
>(BASE_NAME_MAX_LEN): Adjust max length.
>* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_F32_OPS):
>    Add new operand type for BFloat16.
>(vfloat32mf2_t): Ditto.
>(vfloat32m1_t): Ditto.
>(vfloat32m2_t): Ditto.
>(vfloat32m4_t): Ditto.
>(vfloat32m8_t): Ditto.
>* config/riscv/riscv-vector-builtins.cc (DEF_RVV_F32_OPS): Ditto.
>(validate_instance_type_required_extensions):
>    Add required_ext checking for 'Zvfbfmin' and 'Zvfbfwma'.
>* config/riscv/riscv-vector-builtins.h (enum required_ext):
>    Add required_ext declaration for 'Zvfbfmin' and 'Zvfbfwma'.
>(reqired_ext_to_isa_name): Ditto.
>(required_extensions_specified): Ditto.
>(struct function_group_info): Add match case for 'Zvfbfmin' and 'Zvfbfwma'.
>* config/riscv/riscv.cc (riscv_validate_vector_type):
>    Add required_ext checking for 'Zvfbfmin' and 'Zvfbfwma'.
>
>---
>.../riscv/riscv-vector-builtins-bases.cc  | 69 +++
>.../riscv/riscv-vector-builtins-bases.h   |  7 ++
>.../riscv/riscv-vector-builtins-functions.def | 15 
>.../riscv/riscv-vector-builtins-shapes.cc | 37 --
>.../riscv/riscv-vector-builtins-types.def | 13 
>gcc/config/riscv/riscv-vector-builtins.cc | 64 +
>gcc/config/riscv/riscv-vector-builtins.h  | 14 
>gcc/config/riscv/riscv.cc |  5 +-
>8 files changed, 218 insertions(+), 6 deletions(-)
>
>diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
>b/gcc/config/riscv/riscv-vector-builtins-bases.cc
>index b6f6e4ff37e..b10a83ab1fd 100644
>--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
>+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
>@@ -2424,6 +2424,60 @@ public:
>   }
>};
>+/* Implements vfncvtbf16_f. */
>+template
>+class vfncvtbf16_f : public function_base
>+{
>+public:
>+  bool has_rounding_mode_operand_p () const override
>+  {
>+    return FRM_OP == HAS_FRM;
>+  }
>+
>+  bool may_require_frm_p () const override { return true; }
>+
>+  rtx expand (function_expander &e) const override
>+  {
>+    return e.use_exact_insn (code_for_pred_trunc_to_bf16 (e.vector_mode ()));
>+  }
>+};
>+
>+/* Implements vfwcvtbf16_f. */
>+class vfwcvtbf16_f : public function_base
>+{
>+public:
>+  rtx expand (function_expander &e) const override
>+  {
>+    return e.use_exact_insn (code_for_pred_extend_bf16_to (e.vector_mode ()));
>+  }
>+};
>+
>+/* Implements vfwmaccbf16. */
>+template
>+class vfwmaccbf16 : public function_base
>+{
>+public:
>+  bool has_rounding_mode_operand_p () const override
>+  {
>+    return FRM_OP == HAS_FRM;
>+  }
>+
>+  bool may_require_frm_p () const override { return true; }
>+
>+  bool has_merge_operand_p () const override { return false; }
>+
>+  rtx expand (function_expander &e) const override
>+  {
>+    if (e.op_info->op == OP_TYPE_vf)
>+  return e.use_widen_ternop_insn (
>+    code_for_pred_widen_bf16_mul_scalar (e.vector_mode ()));
>+    if (e.op_info->op == OP_TYPE_vv)
>+  return e.use_widen_ternop_insn (
>+    code_for_pred_widen_bf16_mul (e.vector_mode ()));
>+    gcc_un

回复: Re: [PATCH v2] RISC-V:Auto vect for vector-bfloat16

2024-10-22 Thread wangf...@eswincomputing.com

On 2024-10-18 17:53  钟居哲  wrote:
>
>Could you add run test case (verified by QEMU or SPIKE ) ?
> 
I added the run test case with qemu, then I found maybe another change should 
be modified at the same time,
I should add the qemu flag(zvfbfmin and zvfbfwma) in march-to-cpu-opt python 
script.,
@Kito, should I submit the script change on GitHub?
Thanks.
>
>
>juzhe.zh...@rivai.ai
>
>From: Feng Wang
>Date: 2024-10-18 15:24
>To: gcc-patches
>CC: kito.cheng; juzhe.zhong; Feng Wang
>Subject: [PATCH v2] RISC-V:Auto vect for vector-bfloat16
>This patch add auto-vect patterns for vector-bfloat16 extension.
>Similar to vector extensions, these patterns can use vector
>BF16 instructions to optimize the automatic vectorization of for loops.
>gcc/ChangeLog:
>
>* config/riscv/autovec-opt.md (*widen_bf16_fma):
>Add vfwmacc auto-vect opt pattern for vector-bfloat16.
>* config/riscv/vector-bfloat16.md (extend2):
>Add auto-vect pattern for Zvfbfmin extension.
>(trunc2): Ditto.
>* config/riscv/vector-iterators.md:
>Move vector-bfloat16 iterator definitions from vector-bfloat16.md.
>
>gcc/testsuite/ChangeLog:
>
>* gcc.target/riscv/rvv/autovec/vfncvt-auto-vect.c: New test.
>* gcc.target/riscv/rvv/autovec/vfwcvt-auto-vect.c: New test.
>* gcc.target/riscv/rvv/autovec/vfwmacc-auto-vect.c: New test.
>
>Signed-off-by: Feng Wang 
>---
>gcc/config/riscv/autovec-opt.md   |  23 
>gcc/config/riscv/vector-bfloat16.md   | 116 +-
>gcc/config/riscv/vector-iterators.md  |  32 +
>.../riscv/rvv/autovec/vfncvt-auto-vect.c  |  19 +++
>.../riscv/rvv/autovec/vfwcvt-auto-vect.c  |  19 +++
>.../riscv/rvv/autovec/vfwmacc-auto-vect.c |  14 +++
>6 files changed, 195 insertions(+), 28 deletions(-)
>create mode 100644 
>gcc/testsuite/gcc.target/riscv/rvv/autovec/vfncvt-auto-vect.c
>create mode 100644 
>gcc/testsuite/gcc.target/riscv/rvv/autovec/vfwcvt-auto-vect.c
>create mode 100644 
>gcc/testsuite/gcc.target/riscv/rvv/autovec/vfwmacc-auto-vect.c
>
>diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
>index 4b33a145c17..0c6722601ff 100644
>--- a/gcc/config/riscv/autovec-opt.md
>+++ b/gcc/config/riscv/autovec-opt.md
>@@ -1009,6 +1009,29 @@
>   }
>   [(set_attr "type" "vfwmuladd")])
>+;; vfwmacc for vector_bfloat16
>+(define_insn_and_split "*widen_bf16_fma"
>+  [(set (match_operand:VWEXTF_ZVFBF 0 "register_operand")
>+    (plus:VWEXTF_ZVFBF
>+   (mult:VWEXTF_ZVFBF
>+    (float_extend:VWEXTF_ZVFBF
>+   (match_operand: 2 "register_operand"))
>+    (float_extend:VWEXTF_ZVFBF
>+   (match_operand: 3 "register_operand")))
>+   (match_operand:VWEXTF_ZVFBF 1 "register_operand")))]
>+  "TARGET_ZVFBFWMA && can_create_pseudo_p ()"
>+  "#"
>+  "&& 1"
>+  [(const_int 0)]
>+  {
>+    rtx ops[] = {operands[0], operands[1], operands[2], operands[3]};
>+    riscv_vector::emit_vlmax_insn (code_for_pred_widen_bf16_mul (mode),
>+    riscv_vector::WIDEN_TERNARY_OP_FRM_DYN, ops);
>+    DONE;
>+  }
>+  [(set_attr "type" "vfwmaccbf16")
>+   (set_attr "mode" "")])
>+
>;; This combine pattern does not correspond to an single instruction.
>;; This is a temporary pattern produced by a combine pass and if there
>;; is no further combine into widen pattern, then fall back to extend
>diff --git a/gcc/config/riscv/vector-bfloat16.md 
>b/gcc/config/riscv/vector-bfloat16.md
>index 562aa8ee5ed..90b174be2e7 100644
>--- a/gcc/config/riscv/vector-bfloat16.md
>+++ b/gcc/config/riscv/vector-bfloat16.md
>@@ -17,26 +17,11 @@
>;; along with GCC; see the file COPYING3.  If not see
>;; .
>-(define_mode_iterator VWEXTF_ZVFBF [
>-  (RVVM8SF  "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32")
>-  (RVVM4SF  "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32")
>-  (RVVM2SF  "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32")
>-  (RVVM1SF  "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32")
>-  (RVVMF2SF "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32 && 
>TARGET_MIN_VLEN > 32")
>-])
>-
>-(define_mode_attr V_FP32TOBF16_TRUNC [
>-  (RVVM8SF "RVVM4BF") (RVVM4SF "RVVM2BF") (RVVM2SF "RVVM1BF") (RVVM1SF 
>"RVVMF2BF") (RVVMF2SF "RVVMF4BF")
>-])
>-
>-(define_mode_attr VF32_SUBEL [
>-   (RVVM8SF "BF") (RVVM4SF "BF") (RVVM2SF "BF") (RVVM1SF "BF") (RVVMF2SF 
>"BF")])
>-
>;; Zvfbfmin extension
>(define_insn "@pred_trunc_to_bf16"
>-  [(set (match_operand: 0 "register_operand"   "=vd, vd, 
>vr, vr,  &vr,  &vr")
>- (if_then_else:
>+  [(set (match_operand: 0 "register_operand"   "=vd, 
>vd, vr, vr,  &vr,  &vr")
>+ (if_then_else:
>    (unspec:
>  [(match_operand: 1 "vector_mask_operand"  " vm, 
>vm,Wc1,Wc1,vmWc1,vmWc1")
>   (match_operand 4 "vector_length_operand" " rK, rK, 
>rK, rK,   rK,   rK")
>@@ -47,13 +32,13 @@
>   (reg:SI VL_REGNUM)
>   (reg:SI VTYPE_REGNUM)
>   (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
>-   (float_truncate:
>+   (float_truncate:
>   (matc

Re: Re: [PATCH v2] RISC-V:Auto vect for vector-bfloat16

2024-11-12 Thread wangf...@eswincomputing.com

On 2024-11-13 07:30  Edwin Lu  wrote:
>
>I took a look at the CI errors today since I remember Jeff checking the
>CI output. I don't remember if the errors were the main things blocking
>the patch or if there just wasn't any follow up. 
Juzhe suggested me to addd some run test case for this patch, but the run case 
depends on the qemu flag in the script.
So I will submmit a change for "march-to-cpu-opt" firstly and then update this 
patch for the test case.
At the same time, I will merg these case into vector test case, so this issue 
would not be haapened.
Thanks.
>
>I'll look into having the CI output some additional test log information
>to make understanding failures a lot more user friendly but for now, all
>of the (test for excess errors) are "error: 'for' loop initial
>declarations are only allowed in C99 or C11 mode".
>
>https://github.com/ewlu/gcc-precommit-ci/issues/2407#issuecomment-2421766160
>
>Edwin 
>
>On 10/18/2024 12:24 AM, Feng Wang wrote:
>> This patch add auto-vect patterns for vector-bfloat16 extension.
>> Similar to vector extensions, these patterns can use vector
>> BF16 instructions to optimize the automatic vectorization of for loops.
>> gcc/ChangeLog:
>>
>> * config/riscv/autovec-opt.md (*widen_bf16_fma):
>> Add vfwmacc auto-vect opt pattern for vector-bfloat16.
>> * config/riscv/vector-bfloat16.md (extend2):
>> Add auto-vect pattern for Zvfbfmin extension.
>> (trunc2): Ditto.
>> * config/riscv/vector-iterators.md:
>> Move vector-bfloat16 iterator definitions from vector-bfloat16.md.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/rvv/autovec/vfncvt-auto-vect.c: New test.
>> * gcc.target/riscv/rvv/autovec/vfwcvt-auto-vect.c: New test.
>> * gcc.target/riscv/rvv/autovec/vfwmacc-auto-vect.c: New test.
>>
>> Signed-off-by: Feng Wang 
>> ---
>>   gcc/config/riscv/autovec-opt.md   |  23 
>>   gcc/config/riscv/vector-bfloat16.md   | 116 +-
>>   gcc/config/riscv/vector-iterators.md  |  32 +
>>   .../riscv/rvv/autovec/vfncvt-auto-vect.c  |  19 +++
>>   .../riscv/rvv/autovec/vfwcvt-auto-vect.c  |  19 +++
>>   .../riscv/rvv/autovec/vfwmacc-auto-vect.c |  14 +++
>>   6 files changed, 195 insertions(+), 28 deletions(-)
>>   create mode 100644 
>>gcc/testsuite/gcc.target/riscv/rvv/autovec/vfncvt-auto-vect.c
>>   create mode 100644 
>>gcc/testsuite/gcc.target/riscv/rvv/autovec/vfwcvt-auto-vect.c
>>   create mode 100644 
>>gcc/testsuite/gcc.target/riscv/rvv/autovec/vfwmacc-auto-vect.c
>>
>> diff --git a/gcc/config/riscv/autovec-opt.md 
>> b/gcc/config/riscv/autovec-opt.md
>> index 4b33a145c17..0c6722601ff 100644
>> --- a/gcc/config/riscv/autovec-opt.md
>> +++ b/gcc/config/riscv/autovec-opt.md
>> @@ -1009,6 +1009,29 @@
>> }
>> [(set_attr "type" "vfwmuladd")])
>>  
>> +;; vfwmacc for vector_bfloat16
>> +(define_insn_and_split "*widen_bf16_fma"
>> +  [(set (match_operand:VWEXTF_ZVFBF 0 "register_operand")
>> +    (plus:VWEXTF_ZVFBF
>> +  (mult:VWEXTF_ZVFBF
>> +    (float_extend:VWEXTF_ZVFBF
>> +  (match_operand: 2 "register_operand"))
>> +    (float_extend:VWEXTF_ZVFBF
>> +  (match_operand: 3 "register_operand")))
>> +  (match_operand:VWEXTF_ZVFBF 1 "register_operand")))]
>> +  "TARGET_ZVFBFWMA && can_create_pseudo_p ()"
>> +  "#"
>> +  "&& 1"
>> +  [(const_int 0)]
>> +  {
>> +    rtx ops[] = {operands[0], operands[1], operands[2], operands[3]};
>> +    riscv_vector::emit_vlmax_insn (code_for_pred_widen_bf16_mul 
>> (mode),
>> +   riscv_vector::WIDEN_TERNARY_OP_FRM_DYN, ops);
>> +    DONE;
>> +  }
>> +  [(set_attr "type" "vfwmaccbf16")
>> +   (set_attr "mode" "")])
>> +
>>   ;; This combine pattern does not correspond to an single instruction.
>>   ;; This is a temporary pattern produced by a combine pass and if there
>>   ;; is no further combine into widen pattern, then fall back to extend
>> diff --git a/gcc/config/riscv/vector-bfloat16.md 
>> b/gcc/config/riscv/vector-bfloat16.md
>> index 562aa8ee5ed..90b174be2e7 100644
>> --- a/gcc/config/riscv/vector-bfloat16.md
>> +++ b/gcc/config/riscv/vector-bfloat16.md
>> @@ -17,26 +17,11 @@
>>   ;; along with GCC; see the file COPYING3.  If not see
>> ;; .
>>  
>> -(define_mode_iterator VWEXTF_ZVFBF [
>> -  (RVVM8SF  "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32")
>> -  (RVVM4SF  "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32")
>> -  (RVVM2SF  "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32")
>> -  (RVVM1SF  "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32")
>> -  (RVVMF2SF "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32 && 
>> TARGET_MIN_VLEN > 32")
>> -])
>> -
>> -(define_mode_attr V_FP32TOBF16_TRUNC [
>> -  (RVVM8SF "RVVM4BF") (RVVM4SF "RVVM2BF") (RVVM2SF "RVVM1BF") (RVVM1SF 
>> "RVVMF2BF") (RVVMF2SF "RVVMF4BF")
>> -])
>> -
>> -(define_mode_attr VF32_SUBEL [
>> -   (RVVM8SF "BF") (RVVM4SF "BF") (RVVM2SF "BF") (RVVM1SF "BF") (RVVMF2SF 
>> "BF")])
>> -
>>   ;; Zvfbfmi

回复: Re: [PATCH] RISC-V:Fix wrong condition for vector-bfloat16

2024-11-19 Thread wangf...@eswincomputing.com

On 2024-11-20 14:54  钟居哲  wrote:
>
>Are you trying to fix this PR ? 
Yes.
>117669 – RISC-V:The 'VEEWTRUNC4' iterator 'RVVMF2BF' type condition error
>
>I think you should add PR target/117669 in the changelog
> 
OK.
>
>
>
>juzhe.zh...@rivai.ai
>
>From: Feng Wang
>Date: 2024-11-20 14:50
>To: gcc-patches
>CC: kito.cheng; jeffreyalaw; juzhe.zhong; Feng Wang
>Subject: [PATCH] RISC-V:Fix wrong condition for vector-bfloat16
>This patch fix the wrong condition for RVVMF2BF. It should be
>TARGET_VECTOR_ELEN_BF_16.
>gcc/ChangeLog:
>
>* config/riscv/vector-iterators.md: Modify condition.
>
>Signed-off-by: Feng Wang 
>---
>gcc/config/riscv/vector-iterators.md | 2 +-
>1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/gcc/config/riscv/vector-iterators.md 
>b/gcc/config/riscv/vector-iterators.md
>index 6a621459cc4..92cb651ce49 100644
>--- a/gcc/config/riscv/vector-iterators.md
>+++ b/gcc/config/riscv/vector-iterators.md
>@@ -365,7 +365,7 @@
>   (RVVM2BF "TARGET_VECTOR_ELEN_BF_16")
>   (RVVM1BF "TARGET_VECTOR_ELEN_BF_16")
>-  (RVVMF2BF "TARGET_VECTOR_ELEN_FP_16")
>+  (RVVMF2BF "TARGET_VECTOR_ELEN_BF_16")
>   (RVVMF4BF "TARGET_VECTOR_ELEN_BF_16 && TARGET_MIN_VLEN > 32 && 
>TARGET_64BIT")
>   (RVVM2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_64BIT")
>--
>2.17.1
>
>

Re: Re: [PATCH 2/3] RISC-V: Add Zvfbfmin and Zvfbfwma intrinsic

Re: Re: [PATCH 2/3] RISC-V: Add Zvfbfmin and Zvfbfwma intrinsic

Re: Re: [PATCH 3/3 v3] RISC-V: Add md files for vector BFloat16

Re: Re: [RE] [v2] RISC-V: Add Zfbfmin extension

Re: Re: [PATCH 2/3] RISC-V: Add Zvfbfmin and Zvfbfwma intrinsic

回复: Re: [PATCH v2] RISC-V:Auto vect for vector-bfloat16

Re: Re: [PATCH v2] RISC-V:Auto vect for vector-bfloat16

回复: Re: [PATCH] RISC-V:Fix wrong condition for vector-bfloat16

8 matches

Site Navigation

Mail list logo

Footer information