Re: [gem5-dev] Review Request 3747: ruby: Remove RubyMemoryControl and associated files

2016-11-30 Thread Jason Lowe-Power 

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3747/#review9177
---

Ship it!


Ship It!

- Jason Lowe-Power


On Nov. 30, 2016, 4:48 p.m., Andreas Hansson wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3747/
> ---
> 
> (Updated Nov. 30, 2016, 4:48 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11721:60b44b57fecb
> ---
> ruby: Remove RubyMemoryControl and associated files
> 
> This patch removes the deprecated RubyMemoryControl. The DRAMCtrl
> module should be used instead.
> 
> 
> Diffs
> -
> 
>   src/mem/ruby/structures/RubyMemoryControl.py 482900205561 
>   src/mem/ruby/structures/SConscript 482900205561 
>   src/mem/ruby/structures/RubyMemoryControl.hh 482900205561 
>   src/mem/ruby/structures/RubyMemoryControl.cc 482900205561 
>   src/mem/ruby/structures/MemoryNode.hh 482900205561 
>   src/mem/ruby/structures/MemoryNode.cc 482900205561 
>   src/mem/ruby/SConscript 482900205561 
> 
> Diff: http://reviews.gem5.org/r/3747/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Andreas Hansson
> 
>

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[gem5-dev] changeset in gem5: arch: [Patch 1/5] Added RISC-V base instructi...

2016-11-30 Thread Alec Roelke 
changeset 0596db108c53 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0596db108c53
description:
arch: [Patch 1/5] Added RISC-V base instruction set RV64I

First of five patches adding RISC-V to GEM5. This patch introduces the
base 64-bit ISA (RV64I) in src/arch/riscv for use with syscall 
emulation.
The multiply, floating point, and atomic memory instructions will be 
added
in additional patches, as well as support for more detailed CPU models.
The loader is also modified to be able to parse RISC-V ELF files, and a
"Hello world\!" example for RISC-V is added to test-progs.

Patch 2 will implement the multiply extension, RV64M; patch 3 will 
implement
the floating point (single- and double-precision) extensions, RV64FD;
patch 4 will implement the atomic memory instructions, RV64A, and patch 
5
will add support for timing, minor, and detailed CPU models that is 
missing
from the first four patches (such as handling locked memory).

[Removed several unused parameters and imports from RiscvInterrupts.py,
RiscvISA.py, and RiscvSystem.py.]
[Fixed copyright information in RISC-V files copied from elsewhere that 
had
ARM licenses attached.]
[Reorganized instruction definitions in decoder.isa so that they are 
sorted
by opcode in preparation for the addition of ISA extensions M, A, F, D.]
[Fixed formatting of several files, removed some variables and
instructions that were missed when moving them to other patches, fixed
RISC-V Foundation copyright attribution, and fixed history of files
copied from other architectures using hg copy.]
[Fixed indentation of switch cases in isa.cc.]
[Reorganized syscall descriptions in linux/process.cc to remove large
number of repeated unimplemented system calls and added implmementations
to functions that have received them since it process.cc was first
created.]
[Fixed spacing for some copyright attributions.]
[Replaced the rest of the file copies using hg copy.]
[Fixed style check errors and corrected unaligned memory accesses.]
[Fix some minor formatting mistakes.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power 

diffstat:

 build_opts/RISCV   |3 +
 ext/libelf/elf_common.h|1 +
 src/arch/riscv/RiscvISA.py |   50 
 src/arch/riscv/RiscvInterrupts.py  |   39 +++
 src/arch/riscv/RiscvSystem.py  |   37 +++
 src/arch/riscv/RiscvTLB.py |   41 +++
 src/arch/riscv/SConscript  |   72 ++
 src/arch/riscv/SConsopts   |   33 +++
 src/arch/riscv/decoder.cc  |   38 +++
 src/arch/riscv/decoder.hh  |  117 ++
 src/arch/riscv/faults.cc   |   84 +++
 src/arch/riscv/faults.hh   |  151 +
 src/arch/riscv/idle_event.cc   |   44 
 src/arch/riscv/idle_event.hh   |   47 
 src/arch/riscv/interrupts.cc   |   37 +++
 src/arch/riscv/interrupts.hh   |  106 +
 src/arch/riscv/isa.cc  |  233 +
 src/arch/riscv/isa.hh  |  119 ++
 src/arch/riscv/isa/base.isa|   79 +++
 src/arch/riscv/isa/bitfields.isa   |   77 +++
 src/arch/riscv/isa/decoder.isa |  332 ++
 src/arch/riscv/isa/formats/basic.isa   |  100 +
 src/arch/riscv/isa/formats/formats.isa |   42 +++
 src/arch/riscv/isa/formats/mem.isa |  355 
 src/arch/riscv/isa/formats/type.isa|  319 +
 src/arch/riscv/isa/formats/unknown.isa |   80 +++
 src/arch/riscv/isa/includes.isa|   90 
 src/arch/riscv/isa/main.isa|   63 +
 src/arch/riscv/isa/operands.isa|   56 +
 src/arch/riscv/isa_traits.hh   |   74 ++
 src/arch/riscv/kernel_stats.hh |   54 
 src/arch/riscv/linux/linux.cc  |   37 +++
 src/arch/riscv/linux/linux.hh  |  199 ++
 src/arch/riscv/linux/process.cc|  137 
 src/arch/riscv/linux/process.hh|   62 +
 src/arch/riscv/locked_mem.hh   |   77 +++
 src/arch/riscv/microcode_rom.hh|   41 +++
 src/arch/riscv/mmapped_ipr.hh  |   50 
 src/arch/riscv/pagetable.cc|   79 +++
 src/arch/riscv/pagetable.hh|  117 ++
 src/arch/riscv/pra_constants.hh|  330 ++
 src/arch/riscv/process.cc  |  238 +
 src/arch/riscv/process.hh  |   66 ++
 src/arch/riscv/pseudo_inst.hh  |   45 
 src/arch/riscv/registers.hh|  181

[gem5-dev] changeset in gem5: cpu: Remove branch predictor function predict...

2016-11-30 Thread Jason Lowe-Power 
changeset b0853929e223 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b0853929e223
description:
cpu: Remove branch predictor function predictInOrder

This function was used by the now-defunct InOrderCPU model. Since this
model is no longer in gem5, this function was not called from anywhere 
in
the code.

diffstat:

 src/cpu/pred/bpred_unit.cc |  122 -
 src/cpu/pred/bpred_unit.hh |3 -
 2 files changed, 0 insertions(+), 125 deletions(-)

diffs (145 lines):

diff -r 482900205561 -r b0853929e223 src/cpu/pred/bpred_unit.cc
--- a/src/cpu/pred/bpred_unit.ccWed Nov 30 11:15:21 2016 -0500
+++ b/src/cpu/pred/bpred_unit.ccWed Nov 30 17:10:27 2016 -0500
@@ -320,128 +320,6 @@
 return pred_taken;
 }
 
-bool
-BPredUnit::predictInOrder(const StaticInstPtr , const InstSeqNum ,
-  int asid, TheISA::PCState ,
-  TheISA::PCState , ThreadID tid)
-{
-// See if branch predictor predicts taken.
-// If so, get its target addr either from the BTB or the RAS.
-// Save off record of branch stuff so the RAS can be fixed
-// up once it's done.
-
-using TheISA::MachInst;
-
-bool pred_taken = false;
-TheISA::PCState target;
-
-++lookups;
-ppBranches->notify(1);
-
-DPRINTF(Branch, "[tid:%i] [sn:%i] %s ... PC %s doing branch "
-"prediction\n", tid, seqNum,
-inst->disassemble(instPC.instAddr()), instPC);
-
-void *bp_history = NULL;
-
-if (inst->isUncondCtrl()) {
-DPRINTF(Branch, "[tid:%i] Unconditional control.\n", tid);
-pred_taken = true;
-// Tell the BP there was an unconditional branch.
-uncondBranch(tid, instPC.instAddr(), bp_history);
-
-if (inst->isReturn() && RAS[tid].empty()) {
-DPRINTF(Branch, "[tid:%i] RAS is empty, predicting "
-"false.\n", tid);
-pred_taken = false;
-}
-} else {
-++condPredicted;
-
-pred_taken = lookup(tid, predPC.instAddr(), bp_history);
-}
-
-PredictorHistory predict_record(seqNum, predPC.instAddr(), pred_taken,
-bp_history, tid);
-
-// Now lookup in the BTB or RAS.
-if (pred_taken) {
-if (inst->isReturn()) {
-++usedRAS;
-
-// If it's a function return call, then look up the address
-// in the RAS.
-TheISA::PCState rasTop = RAS[tid].top();
-target = TheISA::buildRetPC(instPC, rasTop);
-
-// Record the top entry of the RAS, and its index.
-predict_record.usedRAS = true;
-predict_record.RASIndex = RAS[tid].topIdx();
-predict_record.RASTarget = rasTop;
-
-assert(predict_record.RASIndex < 16);
-
-RAS[tid].pop();
-
-DPRINTF(Branch, "[tid:%i]: Instruction %s is a return, "
-"RAS predicted target: %s, RAS index: %i.\n",
-tid, instPC, target,
-predict_record.RASIndex);
-} else {
-++BTBLookups;
-
-if (inst->isCall()) {
-
-RAS[tid].push(instPC);
-predict_record.pushedRAS = true;
-
-// Record that it was a call so that the top RAS entry can
-// be popped off if the speculation is incorrect.
-predict_record.wasCall = true;
-
-DPRINTF(Branch, "[tid:%i]: Instruction %s was a call"
-", adding %s to the RAS index: %i.\n",
-tid, instPC, predPC,
-RAS[tid].topIdx());
-}
-
-if (inst->isCall() &&
-inst->isUncondCtrl() &&
-inst->isDirectCtrl()) {
-target = inst->branchTarget(instPC);
-} else if (BTB.valid(predPC.instAddr(), asid)) {
-++BTBHits;
-
-// If it's not a return, use the BTB to get the target addr.
-target = BTB.lookup(predPC.instAddr(), asid);
-
-DPRINTF(Branch, "[tid:%i]: [asid:%i] Instruction %s "
-"predicted target is %s.\n",
-tid, asid, instPC, target);
-} else {
-DPRINTF(Branch, "[tid:%i]: BTB doesn't have a "
-"valid entry, predicting false.\n",tid);
-pred_taken = false;
-}
-}
-}
-
-if (pred_taken) {
-// Set the PC and the instruction's predicted target.
-predPC = target;
-}
-DPRINTF(Branch, "[tid:%i]: [sn:%i]: Setting Predicted PC to %s.\n",
-tid, seqNum, predPC);
-
-predHist[tid].push_front(predict_record);
-
-DPRINTF(Branch, "[tid:%i] [sn:%i] pushed onto front of predHist "
-"...predHist.size(): %i\n",
-tid, seqNum, predHist[tid].size());
-
-return

[gem5-dev] changeset in gem5: riscv: [Patch 8/5] Added some regression test...

2016-11-30 Thread Alec Roelke 
changeset 08ab68477ea0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=08ab68477ea0
description:
riscv: [Patch 8/5] Added some regression tests to RISC-V

This patch is the eighth patch in a series adding RISC-V to gem5, and
third of the bonus patches to the original series of five. It adds some
regression tests to RISC-V.

Regression tests included:
- se/00.hello
- se/02.insttest (split into several binaries which are not included due
  to large size)

The tests added to 00.insttest will need to be build manually; to
facilitate this, a Makefile is included. The required toolchain and
compiler (riscv64-unknown-elf-gcc) can be built from the riscv-tools
GitHub repository at https://github.com/riscv/riscv-tools.

Note that because EBREAK only makes sense when gdb is running or while 
in
FS mode, it is not included in the linux-rv64i insttest. ERET is not
included because it does not make sense in SE mode and, in fact, causes
a panic by design.

Note also that not every system call is tested in linux-rv64i; of the 
ones
defined in linux/process.hh, some have been given numbers but not
definitions for the toolchain, or are merely stubs that always return 
0. Of
the ones that do work properly, only a subset are tested due to similar
functionality.

Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power 

diffstat:

 tests/test-progs/hello/bin/riscv/linux/hello   |  Bin 
 tests/test-progs/insttest/src/riscv/Makefile   |   51 +
 tests/test-progs/insttest/src/riscv/insttest.h |   79 ++
 tests/test-progs/insttest/src/riscv/rv64a.cpp  |  192 ++
 tests/test-progs/insttest/src/riscv/rv64a.h|  299 ++
 tests/test-progs/insttest/src/riscv/rv64d.cpp  |  708 +
 tests/test-progs/insttest/src/riscv/rv64d.h|  323 +++
 tests/test-progs/insttest/src/riscv/rv64f.cpp  |  694 
 tests/test-progs/insttest/src/riscv/rv64f.h|  357 
 tests/test-progs/insttest/src/riscv/rv64i.cpp  |  432 +++
 tests/test-progs/insttest/src/riscv/rv64i.h|  440 +++
 tests/test-progs/insttest/src/riscv/rv64m.cpp  |  143 +
 tests/test-progs/insttest/src/riscv/rv64m.h|  144 +
 util/regress   |1 +
 14 files changed, 3863 insertions(+), 0 deletions(-)

diffs (truncated from 3923 to 300 lines):

diff -r f37b5fcd66fe -r 08ab68477ea0 
tests/test-progs/hello/bin/riscv/linux/hello
Binary file tests/test-progs/hello/bin/riscv/linux/hello has changed
diff -r f37b5fcd66fe -r 08ab68477ea0 
tests/test-progs/insttest/src/riscv/Makefile
--- /dev/null   Thu Jan 01 00:00:00 1970 +
+++ b/tests/test-progs/insttest/src/riscv/Makefile  Wed Nov 30 17:12:56 
2016 -0500
@@ -0,0 +1,51 @@
+# Copyright (c) 2016 The University of Virginia
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Alec Roelke
+
+CXX=riscv64-unknown-elf-g++
+CFLAGS=--std=c++11 -O3 -static
+
+TARGETS=rv64i rv64m rv64a rv64f rv64d
+PREFIX=../../bin/riscv/linux
+BIN=insttest
+
+all: $(TARGETS)
+
+$(TARGETS):
+   -mkdir -p $(PREFIX)-$@
+   $(CXX) $< $(CFLAGS) -o $(PREFIX)-$@/$(BIN)
+
+rv64i: rv64i.cpp
+rv64m: rv64m.cpp
+rv64a: rv64a.cpp
+rv64f: rv64f.cpp
+rv64d: rv64d.cpp
+
+clean:
+   -rm $(PREFIX)-*/$(BIN)
+
+.PHONY: all clean
diff -r f37b5fcd66fe -r

[gem5-dev] changeset in gem5: riscv: [Patch 3/5] Added RISCV floating point...

2016-11-30 Thread Alec Roelke 
changeset eb58f1bbeac8 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=eb58f1bbeac8
description:
riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD

Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD
extensions, which include single- and double-precision floating point
instructions.

Patch 1 introduced RISC-V and implemented the base instruction set, 
RV64I
and patch 2 implemented the integer multiply extension, RV64M.

Patch 4 will implement the atomic memory instructions, RV64A, and patch
5 will add support for timing, minor, and detailed CPU models that is
missing from the first four patches.

[Fixed exception handling in floating-point instructions to conform 
better
to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V
simulator.]
[Fixed style errors in decoder.isa.]
[Fixed some fuzz caused by modifying a previous patch.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power 

diffstat:

 src/arch/riscv/faults.cc   |7 +
 src/arch/riscv/faults.hh   |   20 +
 src/arch/riscv/isa/bitfields.isa   |   10 +
 src/arch/riscv/isa/decoder.isa |  829 +
 src/arch/riscv/isa/formats/formats.isa |1 +
 src/arch/riscv/isa/formats/fp.isa  |  136 +
 src/arch/riscv/isa/includes.isa|2 +
 src/arch/riscv/isa/operands.isa|   11 +
 src/arch/riscv/registers.hh|2 +-
 src/arch/riscv/utility.hh  |   40 +
 10 files changed, 1057 insertions(+), 1 deletions(-)

diffs (truncated from 1183 to 300 lines):

diff -r d92c26d481b7 -r eb58f1bbeac8 src/arch/riscv/faults.cc
--- a/src/arch/riscv/faults.cc  Wed Nov 30 17:10:28 2016 -0500
+++ b/src/arch/riscv/faults.cc  Wed Nov 30 17:10:28 2016 -0500
@@ -72,6 +72,13 @@
 }
 
 void
+IllegalFrmFault::invoke_se(ThreadContext *tc, const StaticInstPtr )
+{
+panic("Illegal floating-point rounding mode 0x%x at pc 0x%016llx.",
+frm, tc->pcState().pc());
+}
+
+void
 BreakpointFault::invoke_se(ThreadContext *tc, const StaticInstPtr )
 {
 schedRelBreak(0);
diff -r d92c26d481b7 -r eb58f1bbeac8 src/arch/riscv/faults.hh
--- a/src/arch/riscv/faults.hh  Wed Nov 30 17:10:28 2016 -0500
+++ b/src/arch/riscv/faults.hh  Wed Nov 30 17:10:28 2016 -0500
@@ -40,6 +40,12 @@
 namespace RiscvISA
 {
 
+const uint32_t FloatInexact = 1 << 0;
+const uint32_t FloatUnderflow = 1 << 1;
+const uint32_t FloatOverflow = 1 << 2;
+const uint32_t FloatDivZero = 1 << 3;
+const uint32_t FloatInvalid = 1 << 4;
+
 enum ExceptionCode {
 INST_ADDR_MISALIGNED = 0,
 INST_ACCESS = 1,
@@ -124,6 +130,20 @@
 invoke_se(ThreadContext *tc, const StaticInstPtr );
 };
 
+class IllegalFrmFault: public RiscvFault
+{
+  private:
+const uint8_t frm;
+  public:
+IllegalFrmFault(uint8_t r)
+: RiscvFault("Illegal floating-point rounding mode", INST_ILLEGAL,
+SOFTWARE),
+frm(r)
+{}
+
+void invoke_se(ThreadContext *tc, const StaticInstPtr );
+};
+
 class BreakpointFault : public RiscvFault
 {
   public:
diff -r d92c26d481b7 -r eb58f1bbeac8 src/arch/riscv/isa/bitfields.isa
--- a/src/arch/riscv/isa/bitfields.isa  Wed Nov 30 17:10:28 2016 -0500
+++ b/src/arch/riscv/isa/bitfields.isa  Wed Nov 30 17:10:28 2016 -0500
@@ -75,3 +75,13 @@
 // System
 def bitfield FUNCT12 <31:20>;
 def bitfield ZIMM <19:15>;
+
+// Floating point
+def bitfield FD <11:7>;
+def bitfield FS1 <19:15>;
+def bitfield FS2 <24:20>;
+def bitfield FS3 <31:27>;
+
+def bitfield ROUND_MODE <14:12>;
+def bitfield CONV_SGN <24:20>;
+def bitfield FUNCT2 <26:25>;
diff -r d92c26d481b7 -r eb58f1bbeac8 src/arch/riscv/isa/decoder.isa
--- a/src/arch/riscv/isa/decoder.isaWed Nov 30 17:10:28 2016 -0500
+++ b/src/arch/riscv/isa/decoder.isaWed Nov 30 17:10:28 2016 -0500
@@ -61,6 +61,17 @@
 }
 }
 
+0x07: decode FUNCT3 {
+format Load {
+0x2: flw({{
+Fd_bits = (uint64_t)Mem_uw;
+}});
+0x3: fld({{
+Fd_bits = Mem;
+}});
+}
+}
+
 0x0f: decode FUNCT3 {
 format IOp {
 0x0: fence({{
@@ -144,6 +155,17 @@
 }
 }
 
+0x27: decode FUNCT3 {
+format Store {
+0x2: fsw({{
+Mem_uw = (uint32_t)Fs2_bits;
+}});
+0x3: fsd({{
+Mem_ud = Fs2_bits;
+}});
+}
+}
+
 0x33: decode FUNCT3 {
 format ROp {
 0x0: decode FUNCT7 {
@@ -347,6 +369,813 @@
 }
 }
 
+format FPR4Op {
+0x43: decode FUNCT2 {
+0x0: fmadd_s({{
+uint32_t temp;
+float fs1 = reinterpret_cast(temp = Fs1_bits);
+float fs2 = reinterpret_cast(temp = Fs2_bits);
+

[gem5-dev] changeset in gem5: mem: Split the hit_latency into tag_latency a...

2016-11-30 Thread Sophiane Senni 
changeset f15f02d8c79e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f15f02d8c79e
description:
mem: Split the hit_latency into tag_latency and data_latency

If the cache access mode is parallel, i.e. "sequential_access" parameter
is set to "False", tags and data are accessed in parallel. Therefore,
the hit_latency is the maximum latency between tag_latency and
data_latency. On the other hand, if the cache access mode is
sequential, i.e. "sequential_access" parameter is set to "True",
tags and data are accessed sequentially. Therefore, the hit_latency
is the sum of tag_latency plus data_latency.

Signed-off-by: Jason Lowe-Power 

diffstat:

 configs/common/Caches.py  |  12 
 configs/common/O3_ARM_v7a.py  |  12 
 configs/example/arm/devices.py|  15 ++-
 configs/example/memcheck.py   |   5 +++--
 configs/example/memtest.py|   5 +++--
 configs/learning_gem5/part1/caches.py |   6 --
 src/mem/cache/Cache.py|   3 ++-
 src/mem/cache/base.cc |   7 ---
 src/mem/cache/base.hh |   6 ++
 src/mem/cache/tags/Tags.py|  15 ++-
 src/mem/cache/tags/base.cc|   6 +-
 src/mem/cache/tags/base.hh|   8 +++-
 src/mem/cache/tags/base_set_assoc.hh  |  17 -
 src/mem/cache/tags/fa_lru.cc  |  13 -
 src/mem/cache/tags/fa_lru.hh  |   1 +
 15 files changed, 95 insertions(+), 36 deletions(-)

diffs (truncated from 401 to 300 lines):

diff -r b0853929e223 -r f15f02d8c79e configs/common/Caches.py
--- a/configs/common/Caches.py  Wed Nov 30 17:10:27 2016 -0500
+++ b/configs/common/Caches.py  Wed Nov 30 17:10:27 2016 -0500
@@ -48,7 +48,8 @@
 
 class L1Cache(Cache):
 assoc = 2
-hit_latency = 2
+tag_latency = 2
+data_latency = 2
 response_latency = 2
 mshrs = 4
 tgts_per_mshr = 20
@@ -63,7 +64,8 @@
 
 class L2Cache(Cache):
 assoc = 8
-hit_latency = 20
+tag_latency = 20
+data_latency = 20
 response_latency = 20
 mshrs = 20
 tgts_per_mshr = 12
@@ -71,7 +73,8 @@
 
 class IOCache(Cache):
 assoc = 8
-hit_latency = 50
+tag_latency = 50
+data_latency = 50
 response_latency = 50
 mshrs = 20
 size = '1kB'
@@ -79,7 +82,8 @@
 
 class PageTableWalkerCache(Cache):
 assoc = 2
-hit_latency = 2
+tag_latency = 2
+data_latency = 2
 response_latency = 2
 mshrs = 10
 size = '1kB'
diff -r b0853929e223 -r f15f02d8c79e configs/common/O3_ARM_v7a.py
--- a/configs/common/O3_ARM_v7a.py  Wed Nov 30 17:10:27 2016 -0500
+++ b/configs/common/O3_ARM_v7a.py  Wed Nov 30 17:10:27 2016 -0500
@@ -147,7 +147,8 @@
 
 # Instruction Cache
 class O3_ARM_v7a_ICache(Cache):
-hit_latency = 1
+tag_latency = 1
+data_latency = 1
 response_latency = 1
 mshrs = 2
 tgts_per_mshr = 8
@@ -159,7 +160,8 @@
 
 # Data Cache
 class O3_ARM_v7a_DCache(Cache):
-hit_latency = 2
+tag_latency = 2
+data_latency = 2
 response_latency = 2
 mshrs = 6
 tgts_per_mshr = 8
@@ -172,7 +174,8 @@
 # TLB Cache
 # Use a cache as a L2 TLB
 class O3_ARM_v7aWalkCache(Cache):
-hit_latency = 4
+tag_latency = 4
+data_latency = 4
 response_latency = 4
 mshrs = 6
 tgts_per_mshr = 8
@@ -185,7 +188,8 @@
 
 # L2 Cache
 class O3_ARM_v7aL2(Cache):
-hit_latency = 12
+tag_latency = 12
+data_latency = 12
 response_latency = 12
 mshrs = 16
 tgts_per_mshr = 8
diff -r b0853929e223 -r f15f02d8c79e configs/example/arm/devices.py
--- a/configs/example/arm/devices.pyWed Nov 30 17:10:27 2016 -0500
+++ b/configs/example/arm/devices.pyWed Nov 30 17:10:27 2016 -0500
@@ -45,7 +45,8 @@
 from common import CpuConfig
 
 class L1I(L1_ICache):
-hit_latency = 1
+tag_latency = 1
+data_latency = 1
 response_latency = 1
 mshrs = 4
 tgts_per_mshr = 8
@@ -54,7 +55,8 @@
 
 
 class L1D(L1_DCache):
-hit_latency = 2
+tag_latency = 2
+data_latency = 2
 response_latency = 1
 mshrs = 16
 tgts_per_mshr = 16
@@ -64,7 +66,8 @@
 
 
 class WalkCache(PageTableWalkerCache):
-hit_latency = 4
+tag_latency = 4
+data_latency = 4
 response_latency = 4
 mshrs = 6
 tgts_per_mshr = 8
@@ -74,7 +77,8 @@
 
 
 class L2(L2Cache):
-hit_latency = 12
+tag_latency = 12
+data_latency = 12
 response_latency = 5
 mshrs = 32
 tgts_per_mshr = 8
@@ -87,7 +91,8 @@
 class L3(Cache):
 size = '16MB'
 assoc = 16
-hit_latency = 20
+tag_latency = 20
+data_latency = 20
 response_latency = 20
 mshrs = 20
 tgts_per_mshr = 12
diff -r b0853929e223 -r f15f02d8c79e configs/example/memcheck.py
--- a/configs/example/memcheck.py   Wed Nov 30 17:10:27 2016 -0500
+++ b/configs/example/memcheck.py   Wed Nov 30

[gem5-dev] changeset in gem5: riscv: [Patch 5/5] Added missing support for ...

2016-11-30 Thread Alec Roelke 
changeset 055ae402fbd0 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=055ae402fbd0
description:
riscv: [Patch 5/5] Added missing support for timing CPU models

Last of five patches adding RISC-V to GEM5. This patch adds support for
timing, minor, and detailed CPU models that was missing in the last 
four,
which basically consists of handling timing-mode memory accesses and
telling the minor and detailed models what a no-op instruction should
be (addi zero, zero, 0).

Patches 1-4 introduced RISC-V and implemented the base instruction set,
RV64I, and added the multiply, floating point, and atomic memory
extensions, RV64MAFD.

[Fixed compatibility with edit from patch 1.]
[Fixed compatibility with hg copy edit from patch 1.]
[Fixed some style errors in locked_mem.hh.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power 

diffstat:

 build_opts/RISCV |2 +-
 src/arch/riscv/isa_traits.hh |2 +
 src/arch/riscv/locked_mem.hh |  111 ++
 3 files changed, 91 insertions(+), 24 deletions(-)

diffs (167 lines):

diff -r 11950d45640b -r 055ae402fbd0 build_opts/RISCV
--- a/build_opts/RISCV  Wed Nov 30 17:10:28 2016 -0500
+++ b/build_opts/RISCV  Wed Nov 30 17:10:28 2016 -0500
@@ -1,3 +1,3 @@
 TARGET_ISA = 'riscv'
-CPU_MODELS = 'AtomicSimpleCPU'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,MinorCPU,O3CPU'
 PROTOCOL = 'MI_example'
diff -r 11950d45640b -r 055ae402fbd0 src/arch/riscv/isa_traits.hh
--- a/src/arch/riscv/isa_traits.hh  Wed Nov 30 17:10:28 2016 -0500
+++ b/src/arch/riscv/isa_traits.hh  Wed Nov 30 17:10:28 2016 -0500
@@ -63,6 +63,8 @@
 const Addr PageShift = 12;
 const Addr PageBytes = ULL(1) << PageShift;
 
+const ExtMachInst NoopMachInst = 0x0013;
+
 // Memory accesses can not be unaligned
 const bool HasUnalignedMemAcc = false;
 
diff -r 11950d45640b -r 055ae402fbd0 src/arch/riscv/locked_mem.hh
--- a/src/arch/riscv/locked_mem.hh  Wed Nov 30 17:10:28 2016 -0500
+++ b/src/arch/riscv/locked_mem.hh  Wed Nov 30 17:10:28 2016 -0500
@@ -1,7 +1,22 @@
-/*
+/*  
  * Copyright (c) 2006 The Regents of The University of Michigan
  * Copyright (c) 2007-2008 The Florida State University
  * Copyright (c) 2009 The University of Edinburgh
+ * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2014-2015 Sven Karlsson
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2006-2007 The Regents of The University of Michigan
+ * Copyright (c) 2016 The University of Virginia
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -28,47 +43,97 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Steve Reinhardt
- *  Stephen Hines
- *  Timothy M. Jones
+ *  Alec Roelke
  */
-
 #ifndef __ARCH_RISCV_LOCKED_MEM_HH__
 #define __ARCH_RISCV_LOCKED_MEM_HH__
 
-/**
- * @file
- *
- * ISA-specific helper functions for locked memory accesses.
- */
-
+#include "arch/registers.hh"
+#include "base/misc.hh"
+#include "base/trace.hh"
+#include "debug/LLSC.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"
 
+/*
+ * ISA-specific helper functions for locked memory accesses.
+ */
 namespace RiscvISA
 {
+static bool lock_flag = false;
+static Addr lock_addr = 0;
 
 template 
-inline void
-handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
+inline void handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
 {
+if (!lock_flag)
+return;
+
+DPRINTF(LLSC, "Locked snoop on address %x.\n",
+pkt->getAddr());
+
+Addr snoop_addr = pkt->getAddr()
+
+if ((lock_addr) == snoop_addr)
+lock_flag = false;
+}
+
+
+template 
+inline void handleLockedRead(XC *xc, Request *req)
+{
+lock_addr = req->getPaddr()&~0xF;
+lock_flag = true;
+DPRINTF(LLSC, "[cid:%i]: "
+"Load-Link Flag Set & Load-Link Address set to %x.\n",
+req->contextId(), req->getPaddr()&~0xF);
 }
 
 template 
-inline void
-handleLockedRead(XC *xc, Request *req)
-{
-}
+inline void handleLockedSnoopHit(XC *xc)
+{}
 
 template 
-inline void
-handleLockedSnoopHit(XC *xc)
+inline bool handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
 {
-}
+if (req->isUncacheable()) {
+// Funky Turbolaser

[gem5-dev] changeset in gem5: riscv: [Patch 2/5] Added RISC-V multiply exte...

2016-11-30 Thread Alec Roelke 
changeset d92c26d481b7 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d92c26d481b7
description:
riscv: [Patch 2/5] Added RISC-V multiply extension RV64M

Second of five patches adding RISC-V to GEM5.  This patch adds the
RV64M extension, which includes integer multiply and divide 
instructions.

Patch 1 introduced RISC-V and implemented the base instruction set, 
RV64I.

Patch 3 will implement the floating point extensions, RV64FD; patch 4 
will
implement the atomic memory instructions, RV64A; and patch 5 will add
support for timing, minor, and detailed CPU models that is missing from
the first four patches.

[Added mulw instruction that was missed when dividing changes among
patches.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power 

diffstat:

 src/arch/riscv/isa/decoder.isa |  124 +
 1 files changed, 124 insertions(+), 0 deletions(-)

diffs (195 lines):

diff -r 0596db108c53 -r d92c26d481b7 src/arch/riscv/isa/decoder.isa
--- a/src/arch/riscv/isa/decoder.isaWed Nov 30 17:10:28 2016 -0500
+++ b/src/arch/riscv/isa/decoder.isaWed Nov 30 17:10:28 2016 -0500
@@ -150,6 +150,9 @@
 0x0: add({{
 Rd = Rs1_sd + Rs2_sd;
 }});
+0x1: mul({{
+Rd = Rs1_sd*Rs2_sd;
+}}, IntMultOp);
 0x20: sub({{
 Rd = Rs1_sd - Rs2_sd;
 }});
@@ -158,26 +161,93 @@
 0x0: sll({{
 Rd = Rs1 << Rs2<5:0>;
 }});
+0x1: mulh({{
+bool negate = (Rs1_sd < 0) != (Rs2_sd < 0);
+
+uint64_t Rs1_lo = (uint32_t)std::abs(Rs1_sd);
+uint64_t Rs1_hi = (uint64_t)std::abs(Rs1_sd) >> 32;
+uint64_t Rs2_lo = (uint32_t)std::abs(Rs2_sd);
+uint64_t Rs2_hi = (uint64_t)std::abs(Rs2_sd) >> 32;
+
+uint64_t hi = Rs1_hi*Rs2_hi;
+uint64_t mid1 = Rs1_hi*Rs2_lo;
+uint64_t mid2 = Rs1_lo*Rs2_hi;
+uint64_t lo = Rs2_lo*Rs1_lo;
+uint64_t carry = ((uint64_t)(uint32_t)mid1
++ (uint64_t)(uint32_t)mid2 + (lo >> 32)) >> 32;
+
+uint64_t res = hi + (mid1 >> 32) + (mid2 >> 32) + carry;
+Rd = negate ? ~res + (Rs1_sd*Rs2_sd == 0 ? 1 : 0) : res;
+}}, IntMultOp);
 }
 0x2: decode FUNCT7 {
 0x0: slt({{
 Rd = (Rs1_sd < Rs2_sd) ? 1 : 0;
 }});
+0x1: mulhsu({{
+bool negate = Rs1_sd < 0;
+uint64_t Rs1_lo = (uint32_t)std::abs(Rs1_sd);
+uint64_t Rs1_hi = (uint64_t)std::abs(Rs1_sd) >> 32;
+uint64_t Rs2_lo = (uint32_t)Rs2;
+uint64_t Rs2_hi = Rs2 >> 32;
+
+uint64_t hi = Rs1_hi*Rs2_hi;
+uint64_t mid1 = Rs1_hi*Rs2_lo;
+uint64_t mid2 = Rs1_lo*Rs2_hi;
+uint64_t lo = Rs1_lo*Rs2_lo;
+uint64_t carry = ((uint64_t)(uint32_t)mid1
++ (uint64_t)(uint32_t)mid2 + (lo >> 32)) >> 32;
+
+uint64_t res = hi + (mid1 >> 32) + (mid2 >> 32) + carry;
+Rd = negate ? ~res + (Rs1_sd*Rs2 == 0 ? 1 : 0) : res;
+}}, IntMultOp);
 }
 0x3: decode FUNCT7 {
 0x0: sltu({{
 Rd = (Rs1 < Rs2) ? 1 : 0;
 }});
+0x1: mulhu({{
+uint64_t Rs1_lo = (uint32_t)Rs1;
+uint64_t Rs1_hi = Rs1 >> 32;
+uint64_t Rs2_lo = (uint32_t)Rs2;
+uint64_t Rs2_hi = Rs2 >> 32;
+
+uint64_t hi = Rs1_hi*Rs2_hi;
+uint64_t mid1 = Rs1_hi*Rs2_lo;
+uint64_t mid2 = Rs1_lo*Rs2_hi;
+uint64_t lo = Rs1_lo*Rs2_lo;
+uint64_t carry = ((uint64_t)(uint32_t)mid1
++ (uint64_t)(uint32_t)mid2 + (lo >> 32)) >> 32;
+
+Rd = hi + (mid1 >> 32) + (mid2 >> 32) + carry;
+}}, IntMultOp);
 }
 0x4: decode FUNCT7 {
 0x0: xor({{
 Rd = Rs1 ^ Rs2;
 }});
+0x1: div({{
+if (Rs2_sd == 0) {
+Rd_sd = -1;
+} else if (Rs1_sd == std::numeric_limits::min()
+&& Rs2_sd == -1) {
+Rd_sd = std::numeric_limits::min();
+} else {
+Rd_sd = Rs1_sd/Rs2_sd;
+}
+

[gem5-dev] changeset in gem5: riscv: [Patch 7/5] Corrected LRSC semantics

2016-11-30 Thread Alec Roelke 
changeset f37b5fcd66fe in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f37b5fcd66fe
description:
riscv: [Patch 7/5] Corrected LRSC semantics

RISC-V makes use of load-reserved and store-conditional instructions to
enable creation of lock-free concurrent data manipulation as well as
ACQUIRE and RELEASE semantics for memory ordering of LR, SC, and AMO
instructions (the latter of which do not follow LR/SC semantics). This
patch is a correction to patch 4, which added these instructions to the
implementation of RISC-V. It modifies locked_mem.hh and the
implementations of lr.w, sc.w, lr.d, and sc.d to apply the proper gem5
flags and return the proper values.

An important difference between gem5's LLSC semantics and RISC-V's LR/SC
ones, beyond the name, is that gem5 uses 0 to indicate failure and 1 to
indicate success, while RISC-V is the opposite. Strictly speaking, 
RISC-V
uses 0 to indicate success and nonzero to indicate failure where the
value would indicate the error, but currently only 1 is reserved as a
failure code by the ISA reference.

This is the seventh patch in the series which originally consisted of 
five
patches that added the RISC-V ISA to gem5. The original five patches 
added
all of the instructions and added support for more detailed CPU models 
and
the sixth patch corrected the implementations of Linux constants and
structs. There will be an eighth patch that adds some regression tests
for the instructions.

[Removed some commented-out code from locked_mem.hh.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power 

diffstat:

 src/arch/riscv/isa/decoder.isa |4 +-
 src/arch/riscv/isa/formats/mem.isa |7 ++-
 src/arch/riscv/locked_mem.hh   |  107 
 3 files changed, 56 insertions(+), 62 deletions(-)

diffs (181 lines):

diff -r f099627c6750 -r f37b5fcd66fe src/arch/riscv/isa/decoder.isa
--- a/src/arch/riscv/isa/decoder.isaWed Nov 30 17:10:28 2016 -0500
+++ b/src/arch/riscv/isa/decoder.isaWed Nov 30 17:10:28 2016 -0500
@@ -218,12 +218,12 @@
 0x3: decode AMOFUNCT {
 0x2: LoadReserved::lr_d({{
 Rd_sd = Mem_sd;
-}}, aq=AQ, rl=RL);
+}}, mem_flags=LLSC, aq=AQ, rl=RL);
 0x3: StoreCond::sc_d({{
 Mem = Rs2;
 }}, {{
 Rd = result;
-}}, aq=AQ, rl=RL);
+}}, mem_flags=LLSC, inst_flags=IsStoreConditional, aq=AQ, rl=RL);
 format AtomicMemOp {
 0x0: amoadd_d({{Rt_sd = Mem_sd;}}, {{
 Mem_sd = Rs2_sd + Rt_sd;
diff -r f099627c6750 -r f37b5fcd66fe src/arch/riscv/isa/formats/mem.isa
--- a/src/arch/riscv/isa/formats/mem.isaWed Nov 30 17:10:28 2016 -0500
+++ b/src/arch/riscv/isa/formats/mem.isaWed Nov 30 17:10:28 2016 -0500
@@ -363,6 +363,9 @@
 if (fault == NoFault) {
 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
 );
+// RISC-V has the opposite convention gem5 has for success flags,
+// so we invert the result here.
+result = !result;
 }
 
 if (fault == NoFault) {
@@ -385,7 +388,9 @@
 
 %(op_dest_decl)s;
 
-uint64_t result = pkt->req->getExtraData();
+// RISC-V has the opposite convention gem5 has for success flags,
+// so we invert the result here.
+uint64_t result = !pkt->req->getExtraData();
 
 if (fault == NoFault) {
 %(postacc_code)s;
diff -r f099627c6750 -r f37b5fcd66fe src/arch/riscv/locked_mem.hh
--- a/src/arch/riscv/locked_mem.hh  Wed Nov 30 17:10:28 2016 -0500
+++ b/src/arch/riscv/locked_mem.hh  Wed Nov 30 17:10:28 2016 -0500
@@ -48,6 +48,8 @@
 #ifndef __ARCH_RISCV_LOCKED_MEM_HH__
 #define __ARCH_RISCV_LOCKED_MEM_HH__
 
+#include 
+
 #include "arch/registers.hh"
 #include "base/misc.hh"
 #include "base/trace.hh"
@@ -60,80 +62,67 @@
  */
 namespace RiscvISA
 {
-static bool lock_flag = false;
-static Addr lock_addr = 0;
 
-template 
-inline void handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
+const int WARN_FAILURE = 1;
+
+// RISC-V allows multiple locks per hart, but each SC has to unlock the most
+// recent one, so we use a stack here.
+static std::stack locked_addrs;
+
+template  inline void
+handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
 {
-if (!lock_flag)
+if (locked_addrs.empty())
 return;
-
-DPRINTF(LLSC, "Locked snoop on address %x.\n",
-pkt->getAddr());
-
-Addr snoop_addr = pkt->getAddr()
-
-if ((lock_addr) == snoop_addr)
-lock_flag = false;
+Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
+DPRINTF(LLSC, "Locked snoop on address %x.\n",

[gem5-dev] changeset in gem5: riscv: [Patch 6/5] Improve Linux emulation fo...

2016-11-30 Thread Alec Roelke 
changeset f099627c6750 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f099627c6750
description:
riscv: [Patch 6/5] Improve Linux emulation for RISC-V

This is an add-on patch for the original series that implemented RISC-V
that improves the implementation of Linux emulation for SE mode. 
Basically
it cleans up linux/linux.hh by removing constants that haven't been
defined for the RISC-V Linux proxy kernel and rearranging the stat
struct so it aligns with RISC-V's implementation of it. It also adds
placeholders for system calls that have been given numbers in RISC-V
but haven't been given implementations yet. These system calls are
as follows:
- readlinkat
- sigprocmask
- ioctl
- clock_gettime
- getrusage
- getrlimit
- setrlimit

The first five patches implemented RISC-V with the base ISA and 
multiply,
floating point, and atomic extensions and added support for detailed
CPU models with memory timing.

[Fixed incompatibility with changes made from patch 1.]
Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power 

diffstat:

 src/arch/riscv/linux/linux.hh   |  238 ---
 src/arch/riscv/linux/process.cc |   14 +-
 2 files changed, 105 insertions(+), 147 deletions(-)

diffs (truncated from 307 to 300 lines):

diff -r 055ae402fbd0 -r f099627c6750 src/arch/riscv/linux/linux.hh
--- a/src/arch/riscv/linux/linux.hh Wed Nov 30 17:10:28 2016 -0500
+++ b/src/arch/riscv/linux/linux.hh Wed Nov 30 17:10:28 2016 -0500
@@ -36,41 +36,41 @@
 class RiscvLinux : public Linux
 {
   public:
-
-static const int TGT_SIGHUP = 0x01;
-static const int TGT_SIGINT = 0x02;
-static const int TGT_SIGQUIT= 0x03;
-static const int TGT_SIGILL = 0x04;
-static const int TGT_SIGTRAP= 0x05;
-static const int TGT_SIGIOT = 0x06;
-static const int TGT_SIGABRT= 0x06;
-static const int TGT_SIGEMT = 0x07;
-static const int TGT_SIGFPE = 0x08;
-static const int TGT_SIGKILL= 0x09;
-static const int TGT_SIGBUS = 0x0a;
-static const int TGT_SIGSEGV= 0x0b;
-static const int TGT_SIGSYS = 0x0c;
-static const int TGT_SIGPIPE= 0x0d;
-static const int TGT_SIGALRM= 0x0e;
-static const int TGT_SIGTERM= 0x0f;
-static const int TGT_SIGUSR1= 0x10;
-static const int TGT_SIGUSR2= 0x11;
-static const int TGT_SIGCHLD= 0x12;
-static const int TGT_SIGCLD = 0x12;
-static const int TGT_SIGPWR = 0x13;
-static const int TGT_SIGWINCH   = 0x14;
-static const int TGT_SIGURG = 0x15;
-static const int TGT_SIGIO  = 0x16;
-static const int TGT_SIGPOLL= 0x16;
-static const int TGT_SIGSTOP= 0x17;
-static const int TGT_SIGTSTP= 0x18;
-static const int TGT_SIGCONT= 0x19;
-static const int TGT_SIGTTIN= 0x1a;
-static const int TGT_SIGTTOU= 0x1b;
-static const int TGT_SIGVTALRM  = 0x1c;
-static const int TGT_SIGPROF= 0x1d;
-static const int TGT_SIGXCPU= 0x1e;
-static const int TGT_SIGXFSZ= 0x1f;
+static const int TGT_SIGHUP =  1;
+static const int TGT_SIGINT =  2;
+static const int TGT_SIGQUIT=  3;
+static const int TGT_SIGILL =  4;
+static const int TGT_SIGTRAP=  5;
+static const int TGT_SIGABRT=  6;
+static const int TGT_SIGIOT =  6;
+static const int TGT_SIGEMT =  7;
+static const int TGT_SIGFPE =  8;
+static const int TGT_SIGKILL=  9;
+static const int TGT_SIGBUS = 10;
+static const int TGT_SIGSEGV= 11;
+static const int TGT_SIGSYS = 12;
+static const int TGT_SIGPIPE= 13;
+static const int TGT_SIGALRM= 14;
+static const int TGT_SIGTERM= 15;
+static const int TGT_SIGURG = 16;
+static const int TGT_SIGSTOP= 17;
+static const int TGT_SIGTSTP= 18;
+static const int TGT_SIGCONT= 19;
+static const int TGT_SIGCHLD= 20;
+static const int TGT_SIGCLD = 20;
+static const int TGT_SIGTTIN= 21;
+static const int TGT_SIGTTOU= 22;
+static const int TGT_SIGPOLL= 23;
+static const int TGT_SIGIO  = 23;
+static const int TGT_SIGXCPU= 24;
+static const int TGT_SIGXFSZ= 25;
+static const int TGT_SIGVTALRM  = 26;
+static const int TGT_SIGPROF= 27;
+static const int

[gem5-dev] Review Request 3747: ruby: Remove RubyMemoryControl and associated files

2016-11-30 Thread Andreas Hansson 

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3747/
---

Review request for Default.


Repository: gem5


Description
---

Changeset 11721:60b44b57fecb
---
ruby: Remove RubyMemoryControl and associated files

This patch removes the deprecated RubyMemoryControl. The DRAMCtrl
module should be used instead.


Diffs
-

  src/mem/ruby/structures/RubyMemoryControl.py 482900205561 
  src/mem/ruby/structures/SConscript 482900205561 
  src/mem/ruby/structures/RubyMemoryControl.hh 482900205561 
  src/mem/ruby/structures/RubyMemoryControl.cc 482900205561 
  src/mem/ruby/structures/MemoryNode.hh 482900205561 
  src/mem/ruby/structures/MemoryNode.cc 482900205561 
  src/mem/ruby/SConscript 482900205561 

Diff: http://reviews.gem5.org/r/3747/diff/


Testing
---


Thanks,

Andreas Hansson

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[gem5-dev] changeset in gem5: tests: Check for TrafficGen as part of memche...

2016-11-30 Thread Andreas Hansson 
changeset 482900205561 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=482900205561
description:
tests: Check for TrafficGen as part of memcheck regression

Since protobuf is still considered optional we do not always have the
TrafficGen. Check before running the memcheck regression.

diffstat:

 tests/configs/memcheck.py |  7 +++
 1 files changed, 7 insertions(+), 0 deletions(-)

diffs (17 lines):

diff -r e832056deaed -r 482900205561 tests/configs/memcheck.py
--- a/tests/configs/memcheck.py Tue Nov 29 13:04:45 2016 -0500
+++ b/tests/configs/memcheck.py Wed Nov 30 11:15:21 2016 -0500
@@ -39,6 +39,13 @@
 # Authors: Jason Lowe-Power
 #  Andreas Hansson
 
+import m5
+from m5.objects import *
+
+# the traffic generator is only available if we have protobuf support,
+# so potentially skip this test
+require_sim_object("TrafficGen")
+
 # A wrapper around configs/example/memcheck.py
 
 # For some reason, this is implicitly needed by run.py
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Re: [gem5-dev] Review Request 3740: commit 8606171b2c2e65d0b9931ccb4bd2ebc533c55d60

2016-11-30 Thread Andreas Sandberg 

---
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3740/#review9176
---

Ship it!


Ship It!

- Andreas Sandberg


On Nov. 29, 2016, 11:54 p.m., Rahul Thakur wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3740/
> ---
> 
> (Updated Nov. 29, 2016, 11:54 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11708:02ce0fdd4929
> ---
> commit 8606171b2c2e65d0b9931ccb4bd2ebc533c55d60
> Author: Rahul Thakur 
> Date:   Thu Oct 27 20:36:16 2016 -0700
> 
> mem: Refactor CommMonitor stats, add basic atomic mode stats
> 
> Change-Id: I978f1155873b3882e16d9cd74e86400efd9c5e3b
> 
> 
> Diffs
> -
> 
>   src/mem/comm_monitor.hh 1d085f66c4ca 
>   src/mem/comm_monitor.cc 1d085f66c4ca 
> 
> Diff: http://reviews.gem5.org/r/3740/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Rahul Thakur
> 
>

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[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

2016-11-30 Thread Cron Daemon 
* build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO: 
CHANGED!
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: 
passed.
* 
build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer:
 passed.
* build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest: passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: 
passed.
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple:
 passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: passed.
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level:
 passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: passed.
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: 
passed.
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: passed.
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: passed.
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple:
 passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual:
 passed.
* build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: 
passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: passed.
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level:
 passed.
* build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: passed.
* build/NULL/tests/opt/quick/se/51.memcheck/null/none/memcheck: passed.
* 
build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level:
 passed.
* 
build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory:
 passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual:
 passed.
* 
build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token:
 passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: 
passed.
* build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby: 
passed.
* build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: passed.
* build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: passed.
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic: 
passed.
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: passed.
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple:
 passed.
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp:
 passed.
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: 
passed.
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp:
 passed.
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: passed.
* build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: 
passed.
* build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic: passed.
* build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic: passed.
* build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing: passed.
* 
build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level:
 passed.
* build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby: 
passed.
* build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing: passed.
* build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic: passed.
* 
build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple:
 passed.
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: 
passed.
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp:
 passed.
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level:
 passed.
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic: passed.
* build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: 
passed.
* build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing: passed.
* build/X86/tests/opt/quick/se/10.mcf/x86/linux/simple-atomic: 
passed.Delete("build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic/system.terminal")
*